238 lines
12 KiB
C
238 lines
12 KiB
C
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/**
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* @section License
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017, Thomas Barth, barth-dev.de
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __DRIVERS_CAN_REGDEF_H_
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#define __DRIVERS_CAN_REGDEF_H_
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/** \brief Start address of CAN registers */
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#define MODULE_CAN ((volatile CAN_Module_t *)0x3ff6b000)
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/** \brief Interrupt status register */
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typedef enum {
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__CAN_IRQ_RX= BIT(0), /**< \brief RX Interrupt */
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__CAN_IRQ_TX= BIT(1), /**< \brief TX Interrupt */
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__CAN_IRQ_ERR= BIT(2), /**< \brief Error Interrupt */
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__CAN_IRQ_DATA_OVERRUN= BIT(3), /**< \brief Date Overrun Interrupt */
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__CAN_IRQ_WAKEUP= BIT(4), /**< \brief Wakeup Interrupt */
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__CAN_IRQ_ERR_PASSIVE= BIT(5), /**< \brief Passive Error Interrupt */
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__CAN_IRQ_ARB_LOST= BIT(6), /**< \brief Arbitration lost interrupt */
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__CAN_IRQ_BUS_ERR= BIT(7), /**< \brief Bus error Interrupt */
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}__CAN_IRQ_t;
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/** \brief OCMODE options. */
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typedef enum {
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__CAN_OC_BOM= 0b00, /**< \brief bi-phase output mode */
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__CAN_OC_TOM= 0b01, /**< \brief test output mode */
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__CAN_OC_NOM= 0b10, /**< \brief normal output mode */
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__CAN_OC_COM= 0b11, /**< \brief clock output mode */
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}__CAN_OCMODE_t;
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/**
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* CAN controller (SJA1000).
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*/
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typedef struct {
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int RM:1; /**< \brief MOD.0 Reset Mode */
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unsigned int LOM:1; /**< \brief MOD.1 Listen Only Mode */
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unsigned int STM:1; /**< \brief MOD.2 Self Test Mode */
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unsigned int AFM:1; /**< \brief MOD.3 Acceptance Filter Mode */
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unsigned int SM:1; /**< \brief MOD.4 Sleep Mode */
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unsigned int reserved_27:27; /**< \brief \internal Reserved */
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} B;
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} MOD;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int TR:1; /**< \brief CMR.0 Transmission Request */
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unsigned int AT:1; /**< \brief CMR.1 Abort Transmission */
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unsigned int RRB:1; /**< \brief CMR.2 Release Receive Buffer */
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unsigned int CDO:1; /**< \brief CMR.3 Clear Data Overrun */
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unsigned int GTS:1; /**< \brief CMR.4 Go To Sleep */
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unsigned int reserved_27:27; /**< \brief \internal Reserved */
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} B;
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} CMR;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int RBS:1; /**< \brief SR.0 Receive Buffer Status */
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unsigned int DOS:1; /**< \brief SR.1 Data Overrun Status */
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unsigned int TBS:1; /**< \brief SR.2 Transmit Buffer Status */
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unsigned int TCS:1; /**< \brief SR.3 Transmission Complete Status */
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unsigned int RS:1; /**< \brief SR.4 Receive Status */
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unsigned int TS:1; /**< \brief SR.5 Transmit Status */
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unsigned int ES:1; /**< \brief SR.6 Error Status */
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unsigned int BS:1; /**< \brief SR.7 Bus Status */
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} SR;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int RI:1; /**< \brief IR.0 Receive Interrupt */
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unsigned int TI:1; /**< \brief IR.1 Transmit Interrupt */
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unsigned int EI:1; /**< \brief IR.2 Error Interrupt */
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unsigned int DOI:1; /**< \brief IR.3 Data Overrun Interrupt */
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unsigned int WUI:1; /**< \brief IR.4 Wake-Up Interrupt */
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unsigned int EPI:1; /**< \brief IR.5 Error Passive Interrupt */
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unsigned int ALI:1; /**< \brief IR.6 Arbitration Lost Interrupt */
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unsigned int BEI:1; /**< \brief IR.7 Bus Error Interrupt */
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} IR;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int RIE:1; /**< \brief IER.0 Receive Interrupt Enable */
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unsigned int TIE:1; /**< \brief IER.1 Transmit Interrupt Enable */
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unsigned int EIE:1; /**< \brief IER.2 Error Interrupt Enable */
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unsigned int DOIE:1; /**< \brief IER.3 Data Overrun Interrupt Enable */
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unsigned int WUIE:1; /**< \brief IER.4 Wake-Up Interrupt Enable */
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unsigned int EPIE:1; /**< \brief IER.5 Error Passive Interrupt Enable */
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unsigned int ALIE:1; /**< \brief IER.6 Arbitration Lost Interrupt Enable */
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unsigned int BEIE:1; /**< \brief IER.7 Bus Error Interrupt Enable */
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} IER;
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uint32_t RESERVED0;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int BRP:6; /**< \brief BTR0[5:0] Baud Rate Prescaler */
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unsigned int SJW:2; /**< \brief BTR0[7:6] Synchronization Jump Width*/
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} BTR0;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int TSEG1:4; /**< \brief BTR1[3:0] Timing Segment 1 */
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unsigned int TSEG2:3; /**< \brief BTR1[6:4] Timing Segment 2*/
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unsigned int SAM:1; /**< \brief BTR1.7 Sampling*/
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} BTR1;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int OCMODE:2; /**< \brief OCR[1:0] Output Control Mode, see # */
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unsigned int OCPOL0:1; /**< \brief OCR.2 Output Control Polarity 0 */
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unsigned int OCTN0:1; /**< \brief OCR.3 Output Control Transistor N0 */
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unsigned int OCTP0:1; /**< \brief OCR.4 Output Control Transistor P0 */
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unsigned int OCPOL1:1; /**< \brief OCR.5 Output Control Polarity 1 */
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unsigned int OCTN1:1; /**< \brief OCR.6 Output Control Transistor N1 */
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unsigned int OCTP1:1; /**< \brief OCR.7 Output Control Transistor P1 */
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} OCR;
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uint32_t RESERVED1[2];
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int ALC:8; /**< \brief ALC[7:0] Arbitration Lost Capture */
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} ALC;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int ECC:8; /**< \brief ECC[7:0] Error Code Capture */
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} ECC;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int EWLR:8; /**< \brief EWLR[7:0] Error Warning Limit */
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} EWLR;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int RXERR:8; /**< \brief RXERR[7:0] Receive Error Counter */
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} RXERR;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int TXERR:8; /**< \brief TXERR[7:0] Transmit Error Counter */
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} TXERR;
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union {
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struct {
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uint32_t CODE[4]; /**< \brief Acceptance Message ID */
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uint32_t MASK[4]; /**< \brief Acceptance Mask */
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uint32_t RESERVED2[5];
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} ACC; /**< \brief Acceptance filtering */
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struct {
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int DLC:4; /**< \brief [3:0] DLC, Data length container */
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unsigned int unknown_2:2; /**< \brief \internal unknown */
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unsigned int RTR:1; /**< \brief [6:6] RTR, Remote Transmission Request */
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unsigned int FF:1; /**< \brief [7:7] Frame Format */
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} FIR; /**< \brief Frame information record */
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union{
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struct {
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uint32_t ID[2]; /**< \brief Standard frame message-ID*/
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uint32_t data[8]; /**< \brief Standard frame payload */
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uint32_t reserved[2];
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} STD; /**< \brief Standard frame format */
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struct {
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uint32_t ID[4]; /**< \brief Extended frame message-ID*/
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uint32_t data[8]; /**< \brief Extended frame payload */
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} EXT; /**< \brief Extended frame format */
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}TX_RX; /**< \brief RX/TX interface */
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}FCTRL; /**< \brief Function control regs */
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} MBX_CTRL; /**< \brief Mailbox control */
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int RMC:8; /**< \brief RMC[7:0] RX Message Counter */
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unsigned int reserved_24:24; /**< \brief \internal Reserved Enable */
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} B;
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} RMC;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int RBSA:8; /**< \brief RBSA[7:0] RX Buffer Start Address */
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unsigned int reserved_24:24; /**< \brief \internal Reserved Enable */
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} B;
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} RBSA;
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union{uint32_t U; /**< \brief Unsigned access */
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struct {
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unsigned int COD:3; /**< \brief CDR[2:0] CLKOUT frequency selector based of fOSC*/
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unsigned int COFF:1; /**< \brief CDR.3 CLKOUT off*/
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unsigned int reserved_1:1; /**< \brief \internal Reserved */
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unsigned int RXINTEN:1; /**< \brief CDR.5 This bit allows the TX1 output to be used as a dedicated receive interrupt output*/
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unsigned int CBP:1; /**< \brief CDR.6 allows to bypass the CAN input comparator and is only possible in reset mode.*/
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unsigned int CAN_M:1; /**< \brief CDR.7 If CDR.7 is at logic 0 the CAN controller operates in BasicCAN mode. If set to logic 1 the CAN controller operates in PeliCAN mode. Write access is only possible in reset mode*/
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unsigned int reserved_24:24; /**< \brief \internal Reserved */
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} B;
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} CDR;
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uint32_t IRAM[2];
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}CAN_Module_t;
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#endif /* __DRIVERS_CAN_REGDEF_H_ */
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