228 lines
9.3 KiB
C
228 lines
9.3 KiB
C
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/*
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u8g_dev_ssd1325_nhd27oled_gr.c
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2-Bit (gray level) Driver for SSD1325 Controller (OLED Display)
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Rewritten with new architecture
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Tested with NHD-2.7-12864UCY3
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Universal 8bit Graphics Library
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Copyright (c) 2011, olikraus@gmail.com
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this list
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of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or other
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materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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SSD130x Monochrom OLED Controller
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SSD131x Character OLED Controller
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SSD132x Graylevel OLED Controller
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SSD1331 Color OLED Controller
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*/
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#include "u8g.h"
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#define WIDTH 128
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#define HEIGHT 64
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/* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
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static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq[] PROGMEM = {
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U8G_ESC_DLY(10), /* delay 10 ms */
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
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U8G_ESC_CS(1), /* enable chip */
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0x0ae, /* display off, sleep mode */
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0x0b3, 0x091, /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
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0x0a8, 0x03f, /* multiplex ratio: 0x03f * 1/64 duty */
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0x0a2, 0x04c, /* display offset, shift mapping ram counter */
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0x0a1, 0x000, /* display start line */
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0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
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0x0a0, 0x052, /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1), old values: 0x0a0 0x0a6 */
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0x086, /* full current range (0x084, 0x085, 0x086) */
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0x0b8, /* set gray scale table */
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//0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
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0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x077, 0x077, // 4L mode uses 0, 2, 4, 7
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0x081, 0x070, /* contrast, brightness, 0..128, Newhaven: 0x040 */
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0x0b2, 0x051, /* frame frequency (row period) */
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0x0b1, 0x055, /* phase length */
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0x0bc, 0x010, /* pre-charge voltage level */
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0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
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0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
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0x0be, 0x01c, /* VCOMH voltage */
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0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
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0x0a4, /* normal display mode */
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0x0af, /* display on */
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U8G_ESC_DLY(50), /* delay 50 ms */
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_END /* end of sequence */
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};
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static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq[] PROGMEM = {
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_CS(1), /* enable chip */
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0x015, /* column address... */
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0x000, /* start at column 0 */
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0x03f, /* end at column 63 (which is y == 127), because there are two pixel in one column */
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0x075, /* row address... */
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U8G_ESC_END /* end of sequence */
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};
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static void u8g_dev_ssd1325_gr_prepare_row(u8g_t *u8g, u8g_dev_t *dev, uint8_t delta_row)
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{
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uint8_t row = ((u8g_pb_t *)(dev->dev_mem))->p.page;
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row *= ((u8g_pb_t *)(dev->dev_mem))->p.page_height;
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row += delta_row;
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq);
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u8g_WriteByte(u8g, dev, row); /* start at the selected row */
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u8g_WriteByte(u8g, dev, row+1); /* end within the selected row */
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//u8g_SetAddress(u8g, dev, 0); /* instruction mode mode */
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//u8g_WriteByte(u8g, dev, 0x05c); /* write to ram */
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u8g_SetAddress(u8g, dev, 1); /* data mode */
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}
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static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_CS(1), /* enable chip */
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0x0ae, /* display off */
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U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
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U8G_ESC_END /* end of sequence */
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};
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static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_CS(1), /* enable chip */
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0x0af, /* display on */
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U8G_ESC_DLY(50), /* delay 50 ms */
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U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
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U8G_ESC_END /* end of sequence */
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};
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static uint8_t u8g_dev_ssd1325_nhd27oled_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
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{
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switch(msg)
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{
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case U8G_DEV_MSG_INIT:
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u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
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break;
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case U8G_DEV_MSG_STOP:
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break;
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case U8G_DEV_MSG_PAGE_NEXT:
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{
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uint8_t i;
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u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
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uint8_t *p = pb->buf;
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u8g_uint_t cnt;
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cnt = pb->width;
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cnt >>= 2;
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for( i = 0; i < pb->p.page_height; i++ )
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{
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u8g_dev_ssd1325_gr_prepare_row(u8g, dev, i); /* this will also enable chip select */
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u8g_WriteSequence4LTo16GrDevice(u8g, dev, cnt, p);
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u8g_SetChipSelect(u8g, dev, 0);
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p+=cnt;
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}
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}
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break;
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case U8G_DEV_MSG_CONTRAST:
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u8g_SetChipSelect(u8g, dev, 1);
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u8g_SetAddress(u8g, dev, 0); /* instruction mode */
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u8g_WriteByte(u8g, dev, 0x081);
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u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
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u8g_SetChipSelect(u8g, dev, 0);
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return 1;
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case U8G_DEV_MSG_SLEEP_ON:
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
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return 1;
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case U8G_DEV_MSG_SLEEP_OFF:
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
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return 1;
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}
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return u8g_dev_pb8h2_base_fn(u8g, dev, msg, arg);
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}
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static uint8_t u8g_dev_ssd1325_nhd27oled_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
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{
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switch(msg)
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{
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case U8G_DEV_MSG_INIT:
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u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
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break;
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case U8G_DEV_MSG_STOP:
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break;
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case U8G_DEV_MSG_PAGE_NEXT:
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{
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uint8_t i;
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u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
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uint8_t *p = pb->buf;
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u8g_uint_t cnt;
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cnt = pb->width;
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cnt >>= 2;
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for( i = 0; i < pb->p.page_height; i++ )
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{
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u8g_dev_ssd1325_gr_prepare_row(u8g, dev, i); /* this will also enable chip select */
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u8g_WriteSequence4LTo16GrDevice(u8g, dev, cnt, p);
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u8g_SetChipSelect(u8g, dev, 0);
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p+=cnt;
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}
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}
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break;
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case U8G_DEV_MSG_CONTRAST:
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u8g_SetChipSelect(u8g, dev, 1);
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u8g_SetAddress(u8g, dev, 0); /* instruction mode */
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u8g_WriteByte(u8g, dev, 0x081);
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u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
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u8g_SetChipSelect(u8g, dev, 0);
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return 1;
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case U8G_DEV_MSG_SLEEP_ON:
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
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return 1;
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case U8G_DEV_MSG_SLEEP_OFF:
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
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return 1;
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}
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return u8g_dev_pb16h2_base_fn(u8g, dev, msg, arg);
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}
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U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_SW_SPI);
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U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_HW_SPI);
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uint8_t u8g_dev_ssd1325_nhd27oled_2x_buf[WIDTH*2] U8G_NOCOMMON ;
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u8g_pb_t u8g_dev_ssd1325_nhd27oled_2x_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1325_nhd27oled_2x_buf};
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u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_sw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_SW_SPI };
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u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_hw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_HW_SPI };
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