101 lines
3.3 KiB
C
101 lines
3.3 KiB
C
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#ifndef __FLASH_API_H__
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#define __FLASH_API_H__
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#include "rom/spi_flash.h"
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#include "platform.h"
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#define FLASH_SIZE_2MBIT (2 * 1024 * 1024)
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#define FLASH_SIZE_4MBIT (4 * 1024 * 1024)
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#define FLASH_SIZE_8MBIT (8 * 1024 * 1024)
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#define FLASH_SIZE_16MBIT (16 * 1024 * 1024)
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#define FLASH_SIZE_32MBIT (32 * 1024 * 1024)
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#define FLASH_SIZE_64MBIT (64 * 1024 * 1024)
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#define FLASH_SIZE_128MBIT (128 * 1024 * 1024)
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#define FLASH_SIZE_256KBYTE (FLASH_SIZE_2MBIT / 8)
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#define FLASH_SIZE_512KBYTE (FLASH_SIZE_4MBIT / 8)
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#define FLASH_SIZE_1MBYTE (FLASH_SIZE_8MBIT / 8)
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#define FLASH_SIZE_2MBYTE (FLASH_SIZE_16MBIT / 8)
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#define FLASH_SIZE_4MBYTE (FLASH_SIZE_32MBIT / 8)
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#define FLASH_SIZE_8MBYTE (FLASH_SIZE_64MBIT / 8)
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#define FLASH_SIZE_16MBYTE (FLASH_SIZE_128MBIT/ 8)
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# define FLASH_SAFEMODE_ENTER() do{}while(0)
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# define FLASH_SAFEMODE_LEAVE() do{}while(0)
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/******************************************************************************
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* ROM Function definition
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* Note: It is unsafe to use ROM function, but it may efficient.
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* SPIEraseSector
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* SpiFlashOpResult SPIEraseSector(uint16 sec);
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* The 1st parameter is flash sector number.
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* Note: Must disable cache read before using it.
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* SPIRead
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* SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t *des_addr, uint32_t size);
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* The 1st parameter is source addresses.
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* The 2nd parameter is destination addresses.
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* The 3rd parameter is size.
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* Note: Must disable cache read before using it.
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* SPIWrite
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* SpiFlashOpResult SPIWrite(uint32_t des_addr, uint32_t *src_addr, uint32_t size);
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* The 1st parameter is destination addresses.
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* The 2nd parameter is source addresses.
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* The 3rd parameter is size.
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* Note: Must disable cache read before using it.
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*******************************************************************************/
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typedef struct
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{
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uint8_t header_magic;
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uint8_t segment_count;
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enum
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{
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MODE_QIO = 0,
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MODE_QOUT = 1,
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MODE_DIO = 2,
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MODE_DOUT = 15,
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} mode : 8;
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enum
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{
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SPEED_40MHZ = 0,
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SPEED_26MHZ = 1,
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SPEED_20MHZ = 2,
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SPEED_80MHZ = 15,
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} speed : 4;
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enum
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{
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SIZE_4MBIT = 0,
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SIZE_2MBIT = 1,
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SIZE_8MBIT = 2,
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SIZE_16MBIT = 3,
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SIZE_32MBIT = 4,
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SIZE_16MBIT_8M_8M = 5,
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SIZE_32MBIT_8M_8M = 6,
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} size : 4;
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uint32_t entry_point;
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uint32_t memory_offset;
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uint32_t segment_size;
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} PLATFORM_ALIGNMENT_PACKED SPIFlashInfo;
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uint32_t flash_detect_size_byte(void);
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uint32_t flash_safe_get_size_byte(void);
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uint16_t flash_safe_get_sec_num(void);
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SpiFlashOpResult flash_safe_read(uint32 src_addr, uint32 *des_addr, uint32 size);
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SpiFlashOpResult flash_safe_write(uint32 des_addr, uint32 *src_addr, uint32 size);
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SpiFlashOpResult flash_safe_erase_sector(uint16 sec);
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SPIFlashInfo flash_rom_getinfo(void);
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uint8_t flash_rom_get_size_type(void);
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uint32_t flash_rom_get_size_byte(void);
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bool flash_rom_set_size_type(uint8_t);
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bool flash_rom_set_size_byte(uint32_t);
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uint16_t flash_rom_get_sec_num(void);
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uint8_t flash_rom_get_mode(void);
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uint32_t flash_rom_get_speed(void);
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uint8_t byte_of_aligned_array(const uint8_t* aligned_array, uint32_t index);
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uint16_t word_of_aligned_array(const uint16_t *aligned_array, uint32_t index);
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// uint8_t flash_rom_get_checksum(void);
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// uint8_t flash_rom_calc_checksum(void);
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#endif // __FLASH_API_H__
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