2015-01-30 23:23:05 +01:00
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/*
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u8g_dev_ssd1306_128x32.c
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Universal 8bit Graphics Library
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Copyright (c) 2011, olikraus@gmail.com
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this list
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of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or other
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materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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23 Feb 2013: Fixed, Issue 147
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*/
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#include "u8g.h"
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#define WIDTH 128
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#define HEIGHT 32
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#define PAGE_HEIGHT 8
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/* init sequence adafruit 128x32 OLED (NOT TESTED) */
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static const uint8_t u8g_dev_ssd1306_128x32_adafruit1_init_seq[] PROGMEM = {
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
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U8G_ESC_CS(1), /* enable chip */
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0x0ae, /* display off, sleep mode */
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0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
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0x0a8, 0x03f, /* */
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0x0d3, 0x000, /* */
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0x040, /* start line */
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0x08d, 0x010, /* [1] charge pump setting (p62): 0x014 enable, 0x010 disable */
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0x020, 0x000, /* */
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0x0a1, /* segment remap a0/a1*/
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0x0c8, /* c0: scan dir normal, c8: reverse */
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0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
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0x081, 0x09f, /* [1] set contrast control */
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0x0d9, 0x022, /* [1] pre-charge period 0x022/f1*/
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0x0db, 0x040, /* vcomh deselect level */
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0x02e, /* 2012-05-27: Deactivate scroll */
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0x0a4, /* output ram to display */
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0x0a6, /* none inverted normal display mode */
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0x0af, /* display on */
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_END /* end of sequence */
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};
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/* init sequence adafruit 128x32 OLED (NOT TESTED) */
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static const uint8_t u8g_dev_ssd1306_128x32_adafruit2_init_seq[] PROGMEM = {
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
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U8G_ESC_CS(1), /* enable chip */
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0x0ae, /* display off, sleep mode */
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0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
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0x0a8, 0x03f, /* */
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0x0d3, 0x000, /* */
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0x040, /* start line */
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0x08d, 0x014, /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
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0x020, 0x000, /* */
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0x0a1, /* segment remap a0/a1*/
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0x0c8, /* c0: scan dir normal, c8: reverse */
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0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
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0x081, 0x0cf, /* [2] set contrast control */
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0x0d9, 0x0f1, /* [2] pre-charge period 0x022/f1*/
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0x0db, 0x040, /* vcomh deselect level */
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0x02e, /* 2012-05-27: Deactivate scroll */
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0x0a4, /* output ram to display */
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0x0a6, /* none inverted normal display mode */
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0x0af, /* display on */
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_END /* end of sequence */
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};
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/* init sequence adafruit 128x32 OLED (TESTED - WORKING 23.02.13), like adafruit3, but with page addressing mode */
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static const uint8_t u8g_dev_ssd1306_128x32_adafruit3_init_seq[] PROGMEM = {
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
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U8G_ESC_CS(1), /* enable chip */
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0x0ae, /* display off, sleep mode */
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0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
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0x0a8, 0x01f, /* Feb 23, 2013: 128x32 OLED: 0x01f, 128x32 OLED 0x03f */
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0x0d3, 0x000, /* */
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0x040, /* start line */
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0x08d, 0x014, /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
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0x020, 0x002, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), Feb 23, 2013: 128x32 OLED: 0x002, 128x32 OLED 0x012 */
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0x0a1, /* segment remap a0/a1*/
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0x0c8, /* c0: scan dir normal, c8: reverse */
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0x0da, 0x002, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
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0x081, 0x0cf, /* [2] set contrast control */
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0x0d9, 0x0f1, /* [2] pre-charge period 0x022/f1*/
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0x0db, 0x040, /* vcomh deselect level */
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0x02e, /* 2012-05-27: Deactivate scroll */
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0x0a4, /* output ram to display */
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0x0a6, /* none inverted normal display mode */
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0x0af, /* display on */
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_END /* end of sequence */
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};
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/* init sequence Univision datasheet (NOT TESTED) */
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static const uint8_t u8g_dev_ssd1306_128x32_univision_init_seq[] PROGMEM = {
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
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U8G_ESC_CS(1), /* enable chip */
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0x0ae, /* display off, sleep mode */
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0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
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0x0a8, 0x03f, /* multiplex ratio */
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0x0d3, 0x000, /* display offset */
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0x040, /* start line */
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0x08d, 0x010, /* charge pump setting (p62): 0x014 enable, 0x010 disable */
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0x0a1, /* segment remap a0/a1*/
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0x0c8, /* c0: scan dir normal, c8: reverse */
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0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
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0x081, 0x09f, /* set contrast control */
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0x0d9, 0x022, /* pre-charge period */
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0x0db, 0x040, /* vcomh deselect level */
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0x022, 0x000, /* page addressing mode WRONG: 3 byte cmd! */
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0x0a4, /* output ram to display */
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0x0a6, /* none inverted normal display mode */
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0x0af, /* display on */
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_END /* end of sequence */
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};
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/* select one init sequence here */
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//define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_univision_init_seq
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//define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit1_init_seq
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//define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit2_init_seq
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#define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit3_init_seq
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static const uint8_t u8g_dev_ssd1306_128x32_data_start[] PROGMEM = {
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_CS(1), /* enable chip */
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0x010, /* set upper 4 bit of the col adr. to 0 */
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0x000, /* set lower 4 bit of the col adr. to 4 */
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U8G_ESC_END /* end of sequence */
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};
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static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_CS(1), /* enable chip */
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0x0ae, /* display off */
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U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
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U8G_ESC_END /* end of sequence */
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};
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static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_CS(1), /* enable chip */
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0x0af, /* display on */
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U8G_ESC_DLY(50), /* delay 50 ms */
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U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
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U8G_ESC_END /* end of sequence */
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};
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uint8_t u8g_dev_ssd1306_128x32_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
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{
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switch(msg)
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{
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case U8G_DEV_MSG_INIT:
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u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_init_seq);
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break;
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case U8G_DEV_MSG_STOP:
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break;
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case U8G_DEV_MSG_PAGE_NEXT:
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{
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u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_data_start);
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u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (SSD1306) */
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u8g_SetAddress(u8g, dev, 1); /* data mode */
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if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
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return 0;
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u8g_SetChipSelect(u8g, dev, 0);
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}
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break;
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2016-08-02 22:29:34 +02:00
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case U8G_DEV_MSG_CONTRAST:
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u8g_SetChipSelect(u8g, dev, 1);
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u8g_SetAddress(u8g, dev, 0); /* instruction mode */
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u8g_WriteByte(u8g, dev, 0x081);
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u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) ); /* 11 Jul 2015: fixed contrast calculation */
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u8g_SetChipSelect(u8g, dev, 0);
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return 1;
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2015-01-30 23:23:05 +01:00
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case U8G_DEV_MSG_SLEEP_ON:
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
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return 1;
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case U8G_DEV_MSG_SLEEP_OFF:
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
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return 1;
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}
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return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
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}
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uint8_t u8g_dev_ssd1306_128x32_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
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{
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switch(msg)
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{
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case U8G_DEV_MSG_INIT:
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u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_init_seq);
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break;
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case U8G_DEV_MSG_STOP:
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break;
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case U8G_DEV_MSG_PAGE_NEXT:
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{
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u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_data_start);
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u8g_WriteByte(u8g, dev, 0x0b0 | (pb->p.page*2)); /* select current page (SSD1306) */
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u8g_SetAddress(u8g, dev, 1); /* data mode */
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u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
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u8g_SetChipSelect(u8g, dev, 0);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_data_start);
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u8g_WriteByte(u8g, dev, 0x0b0 | (pb->p.page*2+1)); /* select current page (SSD1306) */
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|
|
|
|
u8g_SetAddress(u8g, dev, 1); /* data mode */
|
|
|
|
|
u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
|
|
|
|
|
u8g_SetChipSelect(u8g, dev, 0);
|
|
|
|
|
}
|
|
|
|
|
break;
|
2016-08-02 22:29:34 +02:00
|
|
|
case U8G_DEV_MSG_CONTRAST:
|
|
|
|
|
u8g_SetChipSelect(u8g, dev, 1);
|
|
|
|
|
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
|
|
|
|
|
u8g_WriteByte(u8g, dev, 0x081);
|
|
|
|
|
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) ); /* 11 Jul 2015: fixed contrast calculation */
|
|
|
|
|
u8g_SetChipSelect(u8g, dev, 0);
|
|
|
|
|
return 1;
|
2015-01-30 23:23:05 +01:00
|
|
|
case U8G_DEV_MSG_SLEEP_ON:
|
|
|
|
|
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
|
|
|
|
|
return 1;
|
|
|
|
|
case U8G_DEV_MSG_SLEEP_OFF:
|
|
|
|
|
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
U8G_PB_DEV(u8g_dev_ssd1306_128x32_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x32_fn, U8G_COM_SW_SPI);
|
|
|
|
|
U8G_PB_DEV(u8g_dev_ssd1306_128x32_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x32_fn, U8G_COM_HW_SPI);
|
|
|
|
|
U8G_PB_DEV(u8g_dev_ssd1306_128x32_i2c, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x32_fn, U8G_COM_SSD_I2C);
|
|
|
|
|
|
|
|
|
|
uint8_t u8g_dev_ssd1306_128x32_2x_buf[WIDTH*2] U8G_NOCOMMON ;
|
|
|
|
|
u8g_pb_t u8g_dev_ssd1306_128x32_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1306_128x32_2x_buf};
|
|
|
|
|
u8g_dev_t u8g_dev_ssd1306_128x32_2x_sw_spi = { u8g_dev_ssd1306_128x32_2x_fn, &u8g_dev_ssd1306_128x32_2x_pb, U8G_COM_SW_SPI };
|
|
|
|
|
u8g_dev_t u8g_dev_ssd1306_128x32_2x_hw_spi = { u8g_dev_ssd1306_128x32_2x_fn, &u8g_dev_ssd1306_128x32_2x_pb, U8G_COM_HW_SPI };
|
|
|
|
|
u8g_dev_t u8g_dev_ssd1306_128x32_2x_i2c = { u8g_dev_ssd1306_128x32_2x_fn, &u8g_dev_ssd1306_128x32_2x_pb, U8G_COM_SSD_I2C };
|
