480 lines
14 KiB
C
480 lines
14 KiB
C
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/*
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ucg_dev_ic_ssd1289.c
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Specific code for the ssd1289 controller (TFT displays)
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Universal uC Color Graphics Library
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Copyright (c) 2014, olikraus@gmail.com
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this list
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of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or other
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materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "ucg.h"
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#ifdef NOT_YET_IMPLEMENTED
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static const ucg_pgm_uint8_t ucg_ssd1289_set_pos_seq[] =
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{
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UCG_CS(0), /* enable chip */
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UCG_C10(0x04e), UCG_VARX(0,0x00, 0), UCG_VARX(0,0x0ff, 0), /* set x position */
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UCG_C10(0x04f), UCG_VARY(8,0x01, 0), UCG_VARY(0,0x0ff, 0), /* set y position */
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UCG_C10(0x022), /* write to RAM */
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UCG_DATA(), /* change to data mode */
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UCG_END()
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};
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static const ucg_pgm_uint8_t ucg_ssd1289_set_pos_dir0_seq[] =
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{
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UCG_CS(0), /* enable chip */
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/* last byte: 0x030 horizontal increment (dir = 0) */
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/* last byte: 0x038 vertical increment (dir = 1) */
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/* last byte: 0x000 horizontal deccrement (dir = 2) */
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/* last byte: 0x008 vertical deccrement (dir = 3) */
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UCG_C22(0x000, 0x011, 0x048, 0x030), /* Entry Mode, GRAM write direction and BGR (Bit 12)=1, set TRI (Bit 15) and DFM (Bit 14) --> three byte transfer */
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UCG_C10(0x04e), UCG_VARX(0,0x00, 0), UCG_VARX(0,0x0ff, 0), /* set x position */
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UCG_C10(0x04f), UCG_VARY(8,0x01, 0), UCG_VARY(0,0x0ff, 0), /* set y position */
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UCG_C10(0x022), /* write to RAM */
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UCG_DATA(), /* change to data mode */
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UCG_END()
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};
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static const ucg_pgm_uint8_t ucg_ssd1289_set_pos_dir1_seq[] =
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{
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UCG_CS(0), /* enable chip */
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/* last byte: 0x030 horizontal increment (dir = 0) */
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/* last byte: 0x038 vertical increment (dir = 1) */
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/* last byte: 0x000 horizontal deccrement (dir = 2) */
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/* last byte: 0x008 vertical deccrement (dir = 3) */
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UCG_C22(0x000, 0x011, 0x048, 0x038), /* Entry Mode, GRAM write direction and BGR (Bit 12)=1, set TRI (Bit 15) and DFM (Bit 14) --> three byte transfer */
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UCG_C10(0x04e), UCG_VARX(0,0x00, 0), UCG_VARX(0,0x0ff, 0), /* set x position */
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UCG_C10(0x04f), UCG_VARY(8,0x01, 0), UCG_VARY(0,0x0ff, 0), /* set y position */
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UCG_C10(0x022), /* write to RAM */
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UCG_DATA(), /* change to data mode */
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UCG_END()
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};
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const ucg_pgm_uint8_t ucg_ssd1289_set_pos_dir2_seq[] =
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{
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UCG_CS(0), /* enable chip */
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/* last byte: 0x030 horizontal increment (dir = 0) */
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/* last byte: 0x038 vertical increment (dir = 1) */
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/* last byte: 0x000 horizontal deccrement (dir = 2) */
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/* last byte: 0x008 vertical deccrement (dir = 3) */
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UCG_C22(0x000, 0x011, 0x048, 0x000), /* Entry Mode, GRAM write direction and BGR (Bit 12)=1, set TRI (Bit 15) and DFM (Bit 14) --> three byte transfer */
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UCG_C10(0x020), UCG_VARX(0,0x00, 0), UCG_VARX(0,0x0ff, 0), /* set x position */
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UCG_C10(0x021), UCG_VARY(8,0x01, 0), UCG_VARY(0,0x0ff, 0), /* set y position */
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UCG_C10(0x022), /* write to RAM */
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UCG_DATA(), /* change to data mode */
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UCG_END()
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};
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const ucg_pgm_uint8_t ucg_ssd1289_set_pos_dir3_seq[] =
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{
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UCG_CS(0), /* enable chip */
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/* last byte: 0x030 horizontal increment (dir = 0) */
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/* last byte: 0x038 vertical increment (dir = 1) */
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/* last byte: 0x000 horizontal deccrement (dir = 2) */
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/* last byte: 0x008 vertical deccrement (dir = 3) */
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UCG_C22(0x000, 0x011, 0x048, 0x008), /* Entry Mode, GRAM write direction and BGR (Bit 12)=1, set TRI (Bit 15) and DFM (Bit 14) --> three byte transfer */
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UCG_C10(0x020), UCG_VARX(0,0x00, 0), UCG_VARX(0,0x0ff, 0), /* set x position */
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UCG_C10(0x021), UCG_VARY(8,0x01, 0), UCG_VARY(0,0x0ff, 0), /* set y position */
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UCG_C10(0x022), /* write to RAM */
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UCG_DATA(), /* change to data mode */
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UCG_END()
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};
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ucg_int_t ucg_handle_ssd1289_l90fx(ucg_t *ucg)
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{
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uint8_t c[3];
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if ( ucg_clip_l90fx(ucg) != 0 )
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{
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switch(ucg->arg.dir)
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{
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case 0:
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ucg_com_SendCmdSeq(ucg, ucg_ssd1289_set_pos_dir0_seq);
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break;
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case 1:
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ucg_com_SendCmdSeq(ucg, ucg_ssd1289_set_pos_dir1_seq);
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break;
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case 2:
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ucg_com_SendCmdSeq(ucg, ucg_ssd1289_set_pos_dir2_seq);
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break;
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case 3:
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default:
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ucg_com_SendCmdSeq(ucg, ucg_ssd1289_set_pos_dir3_seq);
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break;
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}
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c[0] = ucg->arg.pixel.rgb.color[0];
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c[1] = ucg->arg.pixel.rgb.color[1];
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c[2] = ucg->arg.pixel.rgb.color[2];
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ucg_com_SendRepeat3Bytes(ucg, ucg->arg.len, c);
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ucg_com_SetCSLineStatus(ucg, 1); /* disable chip */
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return 1;
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}
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return 0;
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}
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/*
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L2TC (Glyph Output)
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Because of this for vertical lines the x min and max values in
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"ucg_ssd1289_set_pos_for_y_seq" are identical to avoid changes of the x position
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*/
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const ucg_pgm_uint8_t ucg_ssd1289_set_x_pos_seq[] =
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{
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UCG_C10(0x020), UCG_VARX(0,0x00, 0), UCG_VARX(0,0x0ff, 0), /* set x position */
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UCG_C10(0x022), /* write to RAM */
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UCG_DATA(), /* change to data mode */
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UCG_END()
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};
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const ucg_pgm_uint8_t ucg_ssd1289_set_y_pos_seq[] =
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{
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UCG_C10(0x021), UCG_VARY(8,0x01, 0), UCG_VARY(0,0x0ff, 0), /* set y position */
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UCG_C10(0x022), /* write to RAM */
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UCG_DATA(), /* change to data mode */
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UCG_END()
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};
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/* without CmdDataSequence */
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ucg_int_t xxxxxx_ucg_handle_ssd1289_l90tc(ucg_t *ucg)
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{
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if ( ucg_clip_l90tc(ucg) != 0 )
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{
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uint8_t buf[3];
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ucg_int_t dx, dy;
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ucg_int_t i;
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const uint8_t *seq;
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unsigned char pixmap;
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uint8_t bitcnt;
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ucg_com_SetCSLineStatus(ucg, 0); /* enable chip */
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ucg_com_SendCmdSeq(ucg, ucg_ssd1289_set_pos_seq);
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switch(ucg->arg.dir)
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{
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case 0:
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dx = 1; dy = 0;
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seq = ucg_ssd1289_set_x_pos_seq;
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break;
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case 1:
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dx = 0; dy = 1;
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seq = ucg_ssd1289_set_y_pos_seq;
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break;
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case 2:
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dx = -1; dy = 0;
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seq = ucg_ssd1289_set_x_pos_seq;
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break;
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case 3:
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default:
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dx = 0; dy = -1;
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seq = ucg_ssd1289_set_y_pos_seq;
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break;
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}
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pixmap = ucg_pgm_read(ucg->arg.bitmap);
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bitcnt = ucg->arg.pixel_skip;
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pixmap <<= bitcnt;
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buf[0] = ucg->arg.pixel.rgb.color[0];
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buf[1] = ucg->arg.pixel.rgb.color[1];
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buf[2] = ucg->arg.pixel.rgb.color[2];
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//ucg_com_SetCSLineStatus(ucg, 0); /* enable chip */
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for( i = 0; i < ucg->arg.len; i++ )
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{
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if ( (pixmap & 128) != 0 )
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{
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ucg_com_SendCmdSeq(ucg, seq);
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ucg_com_SendRepeat3Bytes(ucg, 1, buf);
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}
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pixmap<<=1;
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ucg->arg.pixel.pos.x+=dx;
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ucg->arg.pixel.pos.y+=dy;
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bitcnt++;
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if ( bitcnt >= 8 )
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{
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ucg->arg.bitmap++;
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pixmap = ucg_pgm_read(ucg->arg.bitmap);
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bitcnt = 0;
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}
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}
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ucg_com_SetCSLineStatus(ucg, 1); /* disable chip */
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return 1;
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}
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return 0;
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}
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/* with CmdDataSequence */
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ucg_int_t ucg_handle_ssd1289_l90tc(ucg_t *ucg)
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{
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if ( ucg_clip_l90tc(ucg) != 0 )
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{
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uint8_t buf[16];
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ucg_int_t dx, dy;
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ucg_int_t i;
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unsigned char pixmap;
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uint8_t bitcnt;
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ucg_com_SetCSLineStatus(ucg, 0); /* enable chip */
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ucg_com_SendCmdSeq(ucg, ucg_ssd1289_set_pos_seq);
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switch(ucg->arg.dir)
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{
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case 0:
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dx = 1; dy = 0;
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buf[0] = 0x001; // change to 0 (cmd mode)
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buf[1] = 0x020; // set x
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buf[2] = 0x002; // change to 1 (arg mode)
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buf[3] = 0x000; // upper part x
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buf[4] = 0x000; // no change
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buf[5] = 0x000; // will be overwritten by x value
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buf[6] = 0x001; // change to 0 (cmd mode)
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buf[7] = 0x022; // write data
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buf[8] = 0x002; // change to 1 (data mode)
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buf[9] = 0x000; // red value
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buf[10] = 0x000; // no change
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buf[11] = 0x000; // green value
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buf[12] = 0x000; // no change
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buf[13] = 0x000; // blue value
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break;
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case 1:
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dx = 0; dy = 1;
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buf[0] = 0x001; // change to 0 (cmd mode)
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buf[1] = 0x020; // set y
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buf[2] = 0x002; // change to 1 (arg mode)
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buf[3] = 0x000; // upper part y
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buf[4] = 0x000; // no change
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buf[5] = 0x000; // will be overwritten by y value
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buf[6] = 0x001; // change to 0 (cmd mode)
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buf[7] = 0x022; // write data
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buf[8] = 0x002; // change to 1 (data mode)
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buf[9] = 0x000; // red value
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buf[10] = 0x000; // no change
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buf[11] = 0x000; // green value
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buf[12] = 0x000; // no change
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buf[13] = 0x000; // blue value
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break;
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case 2:
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dx = -1; dy = 0;
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buf[0] = 0x001; // change to 0 (cmd mode)
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buf[1] = 0x020; // set x
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buf[2] = 0x002; // change to 1 (arg mode)
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buf[3] = 0x000; // upper part x
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buf[4] = 0x000; // no change
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buf[5] = 0x000; // will be overwritten by x value
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buf[6] = 0x001; // change to 0 (cmd mode)
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buf[7] = 0x022; // write data
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buf[8] = 0x002; // change to 1 (data mode)
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buf[9] = 0x000; // red value
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buf[10] = 0x000; // no change
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buf[11] = 0x000; // green value
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buf[12] = 0x000; // no change
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buf[13] = 0x000; // blue value
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break;
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case 3:
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default:
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dx = 0; dy = -1;
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buf[0] = 0x001; // change to 0 (cmd mode)
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buf[1] = 0x020; // set y
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buf[2] = 0x002; // change to 1 (arg mode)
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buf[3] = 0x000; // upper part y
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buf[4] = 0x000; // no change
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buf[5] = 0x000; // will be overwritten by y value
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buf[6] = 0x001; // change to 0 (cmd mode)
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buf[7] = 0x022; // write data
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buf[8] = 0x002; // change to 1 (data mode)
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buf[9] = 0x000; // red value
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buf[10] = 0x000; // no change
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buf[11] = 0x000; // green value
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buf[12] = 0x000; // no change
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buf[13] = 0x000; // blue value
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
pixmap = ucg_pgm_read(ucg->arg.bitmap);
|
||
|
|
bitcnt = ucg->arg.pixel_skip;
|
||
|
|
pixmap <<= bitcnt;
|
||
|
|
buf[9] = ucg->arg.pixel.rgb.color[0];
|
||
|
|
buf[11] = ucg->arg.pixel.rgb.color[1];
|
||
|
|
buf[13] = ucg->arg.pixel.rgb.color[2];
|
||
|
|
//ucg_com_SetCSLineStatus(ucg, 0); /* enable chip */
|
||
|
|
|
||
|
|
for( i = 0; i < ucg->arg.len; i++ )
|
||
|
|
{
|
||
|
|
if ( (pixmap & 128) != 0 )
|
||
|
|
{
|
||
|
|
if ( (ucg->arg.dir&1) == 0 )
|
||
|
|
{
|
||
|
|
buf[5] = ucg->arg.pixel.pos.x;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
buf[3] = ucg->arg.pixel.pos.y>>8;
|
||
|
|
buf[5] = ucg->arg.pixel.pos.y&255;
|
||
|
|
}
|
||
|
|
ucg_com_SendCmdDataSequence(ucg, 7, buf);
|
||
|
|
}
|
||
|
|
pixmap<<=1;
|
||
|
|
ucg->arg.pixel.pos.x+=dx;
|
||
|
|
ucg->arg.pixel.pos.y+=dy;
|
||
|
|
bitcnt++;
|
||
|
|
if ( bitcnt >= 8 )
|
||
|
|
{
|
||
|
|
ucg->arg.bitmap++;
|
||
|
|
pixmap = ucg_pgm_read(ucg->arg.bitmap);
|
||
|
|
bitcnt = 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
ucg_com_SetCSLineStatus(ucg, 1); /* disable chip */
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
ucg_int_t ucg_handle_ssd1289_l90se(ucg_t *ucg)
|
||
|
|
{
|
||
|
|
uint8_t i;
|
||
|
|
uint8_t c[3];
|
||
|
|
|
||
|
|
/* Setup ccs for l90se. This will be updated by ucg_clip_l90se if required */
|
||
|
|
|
||
|
|
for ( i = 0; i < 3; i++ )
|
||
|
|
{
|
||
|
|
ucg_ccs_init(ucg->arg.ccs_line+i, ucg->arg.rgb[0].color[i], ucg->arg.rgb[1].color[i], ucg->arg.len);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* check if the line is visible */
|
||
|
|
|
||
|
|
if ( ucg_clip_l90se(ucg) != 0 )
|
||
|
|
{
|
||
|
|
ucg_int_t i;
|
||
|
|
switch(ucg->arg.dir)
|
||
|
|
{
|
||
|
|
case 0:
|
||
|
|
ucg_com_SendCmdSeq(ucg, ucg_ssd1289_set_pos_dir0_seq);
|
||
|
|
break;
|
||
|
|
case 1:
|
||
|
|
ucg_com_SendCmdSeq(ucg, ucg_ssd1289_set_pos_dir1_seq);
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
ucg_com_SendCmdSeq(ucg, ucg_ssd1289_set_pos_dir2_seq);
|
||
|
|
break;
|
||
|
|
case 3:
|
||
|
|
default:
|
||
|
|
ucg_com_SendCmdSeq(ucg, ucg_ssd1289_set_pos_dir3_seq);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
for( i = 0; i < ucg->arg.len; i++ )
|
||
|
|
{
|
||
|
|
c[0] = ucg->arg.ccs_line[0].current;
|
||
|
|
c[1] = ucg->arg.ccs_line[1].current;
|
||
|
|
c[2] = ucg->arg.ccs_line[2].current;
|
||
|
|
ucg_com_SendRepeat3Bytes(ucg, 1, c);
|
||
|
|
ucg_ccs_step(ucg->arg.ccs_line+0);
|
||
|
|
ucg_ccs_step(ucg->arg.ccs_line+1);
|
||
|
|
ucg_ccs_step(ucg->arg.ccs_line+2);
|
||
|
|
}
|
||
|
|
ucg_com_SetCSLineStatus(ucg, 1); /* disable chip */
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
ucg_int_t ucg_dev_ic_ssd1289_18(ucg_t *ucg, ucg_int_t msg, void *data)
|
||
|
|
{
|
||
|
|
switch(msg)
|
||
|
|
{
|
||
|
|
case UCG_MSG_DEV_POWER_UP:
|
||
|
|
/* setup com interface and provide information on the clock speed */
|
||
|
|
/* of the serial and parallel interface. Values are nanoseconds. */
|
||
|
|
return ucg_com_PowerUp(ucg, 40, 100);
|
||
|
|
case UCG_MSG_DEV_POWER_DOWN:
|
||
|
|
/* not yet implemented */
|
||
|
|
return 1;
|
||
|
|
case UCG_MSG_GET_DIMENSION:
|
||
|
|
((ucg_wh_t *)data)->w = 240;
|
||
|
|
((ucg_wh_t *)data)->h = 320;
|
||
|
|
return 1;
|
||
|
|
case UCG_MSG_DRAW_PIXEL:
|
||
|
|
if ( ucg_clip_is_pixel_visible(ucg) !=0 )
|
||
|
|
{
|
||
|
|
uint8_t c[3];
|
||
|
|
ucg_com_SendCmdSeq(ucg, ucg_ssd1289_set_pos_seq);
|
||
|
|
c[0] = ucg->arg.pixel.rgb.color[0];
|
||
|
|
c[1] = ucg->arg.pixel.rgb.color[1];
|
||
|
|
c[2] = ucg->arg.pixel.rgb.color[2];
|
||
|
|
ucg_com_SendRepeat3Bytes(ucg, 1, c);
|
||
|
|
ucg_com_SetCSLineStatus(ucg, 1); /* disable chip */
|
||
|
|
}
|
||
|
|
return 1;
|
||
|
|
case UCG_MSG_DRAW_L90FX:
|
||
|
|
ucg_handle_l90fx(ucg, ucg_dev_ic_ssd1289_18);
|
||
|
|
//ucg_handle_ssd1289_l90fx(ucg);
|
||
|
|
return 1;
|
||
|
|
#ifdef UCG_MSG_DRAW_L90TC
|
||
|
|
case UCG_MSG_DRAW_L90TC:
|
||
|
|
ucg_handle_l90tc(ucg, ucg_dev_ic_ssd1289);
|
||
|
|
//ucg_handle_ssd1289_l90tc(ucg);
|
||
|
|
return 1;
|
||
|
|
#endif /* UCG_MSG_DRAW_L90TC */
|
||
|
|
#ifdef UCG_MSG_DRAW_L90BF
|
||
|
|
case UCG_MSG_DRAW_L90BF:
|
||
|
|
ucg_handle_l90bf(ucg, ucg_dev_ic_ssd1289);
|
||
|
|
return 1;
|
||
|
|
#endif /* UCG_MSG_DRAW_L90BF */
|
||
|
|
/* msg UCG_MSG_DRAW_L90SE is handled by ucg_dev_default_cb */
|
||
|
|
/*
|
||
|
|
case UCG_MSG_DRAW_L90SE:
|
||
|
|
return ucg->ext_cb(ucg, msg, data);
|
||
|
|
*/
|
||
|
|
}
|
||
|
|
return ucg_dev_default_cb(ucg, msg, data);
|
||
|
|
}
|
||
|
|
|
||
|
|
ucg_int_t ucg_ext_ssd1289_18(ucg_t *ucg, ucg_int_t msg, void *data)
|
||
|
|
{
|
||
|
|
switch(msg)
|
||
|
|
{
|
||
|
|
case UCG_MSG_DRAW_L90SE:
|
||
|
|
ucg_handle_l90se(ucg, ucg_dev_ic_ssd1289);
|
||
|
|
//ucg_handle_ssd1289_l90se(ucg);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|