166 lines
8.6 KiB
C
166 lines
8.6 KiB
C
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/*
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ucg_dev_tft_240x320_itdb02.c
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ITDB02 Module Shield
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Documentation: code.google.com/p/itdb02/
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Universal uC Color Graphics Library
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Copyright (c) 2014, olikraus@gmail.com
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this list
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of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or other
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materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "ucg.h"
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//static const uint8_t ucg_dev_ssd1351_128x128_init_seq[] PROGMEM = {
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static const ucg_pgm_uint8_t ucg_tft_240x320_ili9325_init_seq[] = {
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UCG_CFG_CD(0,1), /* DC=0 for command mode, DC=1 for data and args */
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UCG_RST(1),
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UCG_CS(1), /* disable chip */
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UCG_DLY_MS(5),
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UCG_RST(0),
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UCG_DLY_MS(5),
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UCG_RST(1),
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UCG_DLY_MS(50),
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UCG_CS(0), /* enable chip */
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//UCG_C22(0x000, 0x001,0x001, 0x000), /* Driver Output Control, bits 8 & 10 */
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//UCG_C22( 0x000, 0x007, 0x001, 0x033), /* Display Control 1: Operate, display ON, Partial image off */
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//UCG_CS(1), /* disable chip */
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//UCG_END(), /* end of sequence */
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UCG_C22(0x000, 0x001,0x001, 0x000), /* Driver Output Control, bits 8 & 10 */
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UCG_C22(0x000, 0x002, 0x007, 0x000), /* LCD Driving Wave Control, bit 9: Set line inversion */
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//UCG_C22(0x000, 0x003, 0x010, 0x030), /* Entry Mode, GRAM write direction and BGR (Bit 12)=1 (16 bit transfer, 65K Mode)*/
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UCG_C22(0x000, 0x003, 0xc0 | 0x010, 0x030), /* Entry Mode, GRAM write direction and BGR (Bit 12)=1, set TRI (Bit 15) and DFM (Bit 14) --> three byte transfer */
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//UCG_C22(0x000, 0x004, 0x000, 0x000), /* Resize register, all 0: no resize */
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UCG_C22(0x000, 0x008, 0x002, 0x007), /* Display Control 2: set the back porch and front porch */
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//UCG_C22(0x000, 0x009, 0x000, 0x000), /* Display Control 3: normal scan */
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//UCG_C22(0x000, 0x00a, 0x000, 0x000), /* Display Control 4: set to "no FMARK output" */
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UCG_C22(0x000, 0x00c, 0x000, 0x000), /* RGB Display Interface Control 1, RIM=10 (3x6 Bit), 12 Jan 14: RIM=00 */
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//UCG_C22(0x000, 0x00d, 0x000, 0x000), /* Frame Maker Position */
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//UCG_C22(0x000, 0x00f, 0x000, 0x000), /* RGB Display Interface Control 2 */
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UCG_C22(0x000, 0x010, 0x000, 0x000), /* Power Control 1: SAP, BT[3:0], AP, DSTB, SLP, STB, actual setting is done below */
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UCG_C22(0x000, 0x011, 0x000, 0x007), /* Power Control 2: DC1[2:0], DC0[2:0], VC[2:0] */
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UCG_C22(0x000, 0x012, 0x000, 0x000), /* Power Control 3: VREG1OUT voltage */
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UCG_C22(0x000, 0x013, 0x000, 0x000), /* Power Control 4: VDV[4:0] for VCOM amplitude */
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UCG_C22(0x000, 0x007, 0x000, 0x001), /* Display Control 1: Operate, but do not display */
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UCG_DLY_MS(100), /* delay 100 ms */ /* ITDB02 none D verion: 50ms */
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UCG_C22( 0x000, 0x010, 0x010, 0x090), /* Power Control 1: SAP, BT[3:0], AP, DSTB, SLP, STB */
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/* 12. Jan 14. Prev value: 0x016, 0x090 */
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/* ITDB02 none D verion: 0x010, 0x090 */
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//UCG_C22( 0x000, 0x010, 0x017, 0x0f0), /* Power Control 1: Setting for max quality & power consumption: SAP(Bit 12)=1, BT[3:0]=7 (max), APE (Bit 8)=1, AP=7 (max), disable sleep: SLP=0, STB=0 */
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UCG_C22( 0x000, 0x011, 0x002, 0x027), /* Power Control 2 VCI ration, step up circuits 1 & 2 */
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UCG_DLY_MS(50), /* delay 50 ms */
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UCG_C22( 0x000, 0x012, 0x000, 0x01f), /* Power Control 3: VCI: External, VCI*1.80 */
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/* 12. Jan 14. Prev value: 0x000, 0x00d */
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UCG_DLY_MS(50), /* delay 50 ms */
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UCG_C22( 0x000, 0x013, 0x015, 0x000), /* Power Control 4: VDV[4:0] for VCOM amplitude */
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/* 12. Jan 14. Prev value: 0x012, 0x009 */
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UCG_C22( 0x000, 0x029, 0x000, 0x027), /* Power Control 7 */
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/* 12. Jan 14. Prev value: 0x000, 0x00a */
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UCG_C22( 0x000, 0x02b, 0x000, 0x00d), /* Frame Rate: 93 */
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//UCG_C22( 0x000, 0x02b, 0x000, 0x00b), /* Frame Rate: 70, too less, some flicker visible */
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UCG_DLY_MS(50), /* delay 50 ms */
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/* Gamma Control, values from iteadstudio.com reference software on google code */
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/*
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UCG_C22(0x00,0x30,0x00,0x00),
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UCG_C22(0x00,0x31,0x07,0x07),
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UCG_C22(0x00,0x32,0x03,0x07),
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UCG_C22(0x00,0x35,0x02,0x00),
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UCG_C22(0x00,0x36,0x00,0x08),
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UCG_C22(0x00,0x37,0x00,0x04),
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UCG_C22(0x00,0x38,0x00,0x00),
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UCG_C22(0x00,0x39,0x07,0x07),
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UCG_C22(0x00,0x3C,0x00,0x02),
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UCG_C22(0x00,0x3D,0x1D,0x04),
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*/
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UCG_C22( 0x000, 0x020, 0x000, 0x000), /* Horizontal GRAM Address Set */
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UCG_C22( 0x000, 0x021, 0x000, 0x000), /* Vertical GRAM Address Set */
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UCG_C22( 0x000, 0x050, 0x000, 0x000), /* Horizontal GRAM Start Address */
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UCG_C22( 0x000, 0x051, 0x000, 0x0EF), /* Horizontal GRAM End Address: 239 */
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UCG_C22( 0x000, 0x052, 0x000, 0x000), /* Vertical GRAM Start Address */
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UCG_C22( 0x000, 0x053, 0x001, 0x03F), /* Vertical GRAM End Address: 319 */
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UCG_C22( 0x000, 0x060, 0x0a7, 0x000), /* Driver Output Control 2, NL = 0x027 = 320 lines, GS (bit 15) = 1 */
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UCG_C22( 0x000, 0x061, 0x000, 0x001), /* Base Image Display Control: NDL,VLE = 0 (Disbale Vertical Scroll), REV */
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//UCG_C22( 0x000, 0x06a, 0x000, 0x000), /* Vertical Scroll Control */
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//UCG_C22( 0x000, 0x080, 0x000, 0x000), /* Partial Image 1 Display Position */
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//UCG_C22( 0x000, 0x081, 0x000, 0x000), /* Partial Image 1 RAM Start Address */
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//UCG_C22( 0x000, 0x082, 0x000, 0x000), /* Partial Image 1 RAM End Address */
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//UCG_C22( 0x000, 0x083, 0x000, 0x000), /* Partial Image 2 Display Position */
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//UCG_C22( 0x000, 0x084, 0x000, 0x000), /* Partial Image 2 RAM Start Address */
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//UCG_C22( 0x000, 0x085, 0x000, 0x000), /* Partial Image 2 RAM End Address */
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UCG_C22( 0x000, 0x090, 0x000, 0x010), /* Panel Interface Control 1 */
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UCG_C22( 0x000, 0x092, 0x000, 0x000), /* Panel Interface Control 2 */
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/* 0x006, 0x000 */
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UCG_C22( 0x000, 0x007, 0x001, 0x033), /* Display Control 1: Operate, display ON, Partial image off */
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UCG_DLY_MS(10), /* delay 10 ms */
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/* write test pattern */
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//UCG_C22( 0x000, 0x020, 0x000, 0x000), /* Horizontal GRAM Address Set */
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//UCG_C22( 0x000, 0x021, 0x000, 0x011), /* Vertical GRAM Address Set */
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UCG_C20( 0x000, 0x022), /* Write Data to GRAM */
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UCG_CS(1), /* disable chip */
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UCG_END(), /* end of sequence */
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};
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ucg_int_t ucg_dev_ili9325_18x240x320_itdb02(ucg_t *ucg, ucg_int_t msg, void *data)
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{
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switch(msg)
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{
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case UCG_MSG_DEV_POWER_UP:
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/* 1. Call to the controller procedures to setup the com interface */
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if ( ucg_dev_ic_ili9325_18(ucg, msg, data) == 0 )
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return 0;
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/* 2. Send specific init sequence for this display module */
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ucg_com_SendCmdSeq(ucg, ucg_tft_240x320_ili9325_init_seq);
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return 1;
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case UCG_MSG_DEV_POWER_DOWN:
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/* let do power down by the conroller procedures */
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return ucg_dev_ic_ili9325_18(ucg, msg, data);
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case UCG_MSG_GET_DIMENSION:
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((ucg_wh_t *)data)->w = 240;
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((ucg_wh_t *)data)->h = 320;
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return 1;
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}
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/* all other messages are handled by the controller procedures */
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return ucg_dev_ic_ili9325_18(ucg, msg, data);
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}
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