Rewrite of exception handler, take 2.
Turns out ets_printf() lied to me. When handed an aligned string in flash it did 32bit loads on it instead of the expected 8bit loads, so just silencing the exception was enough to give the appearance of it working.
This commit is contained in:
Johny Mattsson
parent
5eb7b53967
commit
4995bcb9d0
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/*
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* Copyright 2015 Dius Computing Pty Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of the copyright holders nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* @author Johny Mattsson <jmattsson@dius.com.au>
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*/
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/* Minimal handler function for 8/16bit loads from the mapped SPI flash.
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* Called from the overridden UserExceptionVector on exception cause 3.
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*/
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asm(
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".section \".iram0.text\"\n"
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" .align 4\n"
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"store_mask:\n"
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" .word 0x004000\n" /* bit 14 is set on store instructions (see note ^) */
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"align_mask:\n"
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" .word ~3\n" /* mask to get 32bit alignment of addresses */
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".type cause3_handler,@function\n"
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"cause3_handler:\n"
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" wsr a2, EXCSAVE2\n" /* free up a2 for use too */
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" rsr a2, EPC1\n" /* get the program counter that caused the exception */
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" ssa8l a2\n" /* prepare to extract the (unaligned) instruction */
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" l32r a0, align_mask\n"/* prepare mask for 32bit alignment */
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" and a2, a2, a0\n" /* get aligned base address of instruction */
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" l32i a0, a2, 0\n" /* load first part */
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" l32i a2, a2, 4\n" /* load second part */
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" src a0, a2, a0\n" /* faulting instruction now in a0 */
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" l32r a2, store_mask\n"
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" and a0, a0, a2\n" /* test for store bit */
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" bnez a0, 1f\n" /* it's a store, we don't do stores, get out */
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"" /* As it turns out, the ESP8266 happily does 8/16bit */
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/* loads from the mapped SPI flash, but then raises an */
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/* exception anyway; we can simply increment the */
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/* program counter and be our merry way, safe in */
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/* the knowledge that the loads have already been done.*/
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/* Note that this only applies to the SPI flash, not */
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/* internal ROM or IRAM - if we ever want to support */
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/* those we'll need to add the appropriate loading */
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/* logic here. For now I see no need for such support. */
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" rsr a2, EPC1\n" /* read the program counter again */
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" addi a2, a2, 3\n" /* advance program counter past faulting instruction */
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" wsr a2, EPC1\n" /* and store it back */
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" rsr a2, EXCSAVE2\n" /* restore a2 */
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" rsr a0, EXCSAVE1\n" /* restore a0 */
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" rfe\n" /* and done! */
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"1:rsr a2, EXCSAVE2\n" /* we're about to chain, so restore the a2 we clobbered*/
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" ret\n" /* and hop back into the exception vector code */
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);
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/* Note ^) Except for the S32E instruction, but that's not applicable here,
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* so we can happily ignore it.
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*/
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/* Our sneaky override of the UserExceptionVector to allow us to handle 8/16bit
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* loads from SPI flash. MUST BE >= 32bytes compiled, as the next vector starts
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* there.
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*/
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asm(
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".section \".UserExceptionVectorOverride.text\"\n"
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".type _UserExceptionVectorOverride,@function\n"
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".globl _UserExceptionVectorOverride\n"
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"_UserExceptionVectorOverride:\n"
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" wsr a0, EXCSAVE1\n" /* free up a0 for a while */
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" rsr a0, EXCCAUSE\n" /* get the exception cause */
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" bnei a0, 3, 2f\n" /* if not EXCCAUSE_LOAD_STORE_ERROR, chain to rtos */
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" j 1f\n" /* jump past noncode bytes for cause3_handler addr */
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" .align 4\n" /* proper alignment for literals */
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" .literal_position\n" /* the linker will put cause3_handler addr here */
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"1:call0 cause3_handler\n" /* handle loads and rfe, stores will return here */
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"2:rsr a0, EXCSAVE1\n" /* restore a0 before we chain */
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" j _UserExceptionVector\n" /* and off we go to rtos */
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);
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@ -0,0 +1,201 @@
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/*
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* Copyright 2016 Dius Computing Pty Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of the copyright holders nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* @author Johny Mattsson <jmattsson@dius.com.au>
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*/
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/* Exception handler for supporting non-32bit wide loads from mapped SPI flash
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* (well, technically any mapped memory that can do 32bit loads). Pure assembly
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* since the RTOS-SDK does not use the ROM-routines for hooking exception
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* vectors, and thus we don't get the nifty C-wrapper. Without it we need to
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* do all the careful register saving and restoring, and at that point its
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* easier to also do the remaining logic in asm than reimplement the C-wrapper.
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*
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* On entry, a0,a2..a15 + SAR registers are saved into an exception frame kept
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* in RAM. Effectively this is the stack for the handler, as we intentionally
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* leave the real (a1) stack untouched to keep things simple and predictable.
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* Just like the C-wrapper, we do not permit loading into a1 as that is not
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* a valid use-case (the stack pointer is 32bit, nothing less).
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*
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* We "only" handle L8UI, L16UI and L16SI instructions, anything else we chain
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* through to the default SDK handler so it can do its usual error reporting.
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*
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* The handler comprises two parts, the actual UserExceptionVectorOverride
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* and the cause3_handler function. The former is what we wedge in to hook
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* the user exceptions, and it only contains enough logic to redirect cause 3
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* (EXCCAUSE_LOAD_STORE_ERROR) exceptions to the cause3_handler function.
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* All other exception codes are chained straight through to the SDK handler
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* we displaced. The cause3_handler is where the actual work gets done for
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* the load functionality.
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*/
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/* frame save area, a0->a15, but a1=>sar */
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.section ".data"
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.align 4
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frame: .fill 16, 4, 0
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/* macro to apply the stored frame values to regs, we need it twice */
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.macro apply_frame
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l32i a15, a0, 60
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l32i a14, a0, 56
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l32i a13, a0, 52
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l32i a12, a0, 48
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l32i a11, a0, 44
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l32i a10, a0, 40
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l32i a9, a0, 36
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l32i a8, a0, 32
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l32i a7, a0, 28
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l32i a6, a0, 24
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l32i a5, a0, 20
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l32i a4, a0, 16
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l32i a3, a0, 12
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l32i a2, a0, 4
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wsr a2, SAR
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l32i a2, a0, 8
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l32i a0, a0, 0
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.endm
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/* Contants/literals for the cause3_handler function */
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.section ".iram0.text"
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.align 4
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align_mask: .word ~3 /* mask to get 32bit alignment of addresses */
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load_mask: .word 0x00f00f /* mask for load instructions */
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l8ui_match: .word 0x000002 /* post-mask match for 8bit load */
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l16ui_match:.word 0x001002 /* post-mask match for 16bit unsigned load */
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l16si_match:.word 0x009002 /* post-mask match for 16bit signed load */
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.literal_position
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/* Register usage in cause3_handler:
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* a0 exception frame pointer
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* a1 stack (untouched)
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* a2 temp values
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* a3 alignment mask
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* a4 instruction match
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* a5 faulting instruction
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* a6 masked instruction
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* a7 excvaddr
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* a11 temp values
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* a12 temp values
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* a13 epc1
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* a15 extracted value
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*/
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.type cause3_handler,@function
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cause3_handler:
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movi a0, frame /* keep our exception frame pointer in a0 */
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s32i a2, a0, 8 /* save all used and/or relevant registers to frame */
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s32i a3, a0, 12
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s32i a4, a0, 16
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s32i a5, a0, 20
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s32i a6, a0, 24
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s32i a7, a0, 28
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s32i a8, a0, 32
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s32i a9, a0, 36
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s32i a10, a0, 40
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s32i a11, a0, 44
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s32i a12, a0, 48
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s32i a13, a0, 52
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s32i a14, a0, 56
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s32i a15, a0, 60
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rsr a2, EXCSAVE1 /* retrieve original a0 */
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s32i a2, a0, 0 /* save original a0 to frame */
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rsr a2, SAR /* get shift register contents */
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s32i a2, a0, 4 /* save sar to frame in a1 slot */
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rsr a13, EPC1 /* get the program counter that caused the exception */
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ssa8l a13 /* prepare to extract the (unaligned) instruction */
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l32r a3, align_mask /* prepare mask for 32bit alignment */
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and a2, a13, a3 /* get aligned base address of instruction */
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l32i a11, a2, 0 /* load first part */
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l32i a12, a2, 4 /* load second part */
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src a5, a12, a11 /* faulting instruction now in a5 */
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l32r a2, load_mask /* get the mask for the load fields */
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and a6, a2, a5 /* extract the to-match-on fields from the instruction */
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rsr a7, EXCVADDR /* get the attempted address to load from */
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and a2, a7, a3 /* mask down to 32bit alignment */
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l32i a2, a2, 0 /* full word in a2 */
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ssa8l a7 /* set up shift based on excvaddr */
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sra a15, a2 /* right-shifted word, not yet masked */
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l32r a4, l8ui_match /* work out what the faulting instruction is */
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beq a6, a4, 1f
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l32r a4, l16ui_match
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beq a6, a4, 2f
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l32r a4, l16si_match
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beq a6, a4, 2f
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j 9f /* it's not a supported load, we need to chain to SDK */
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1:movi a2, 0xff /* 8bits to keep */
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j 3f
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2:movi a2, 0xffff /* 16bits to keep */
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3:and a15, a15, a2 /* apply mask to get the bits we care about */
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l32r a4, l16si_match /* time to consider need for sign extension */
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bne a6, a4, 4f /* skip sign extension */
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bbci a15, 15, 4f /* no sign to extend */
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movi a2, 0xffff0000 /* manual sign extension since 'sext' op not present */
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or a15, a15, a2 /* sign extend */
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4:movi a2, 0xf0 /* register mask for load instructions */
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and a2, a5, a2 /* extract register field */
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srli a2, a2, 2 /* register number*4, effectively offset into frame */
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beqi a2, 4, 9f /* nope, won't do a1, chain through to SDK instead */
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add a2, a0, a2 /* pointer to correct register slot in frame */
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s32i a15, a2, 0 /* apply new value to stashed register */
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addi a2, a13, 3 /* advance program counter past faulting instruction */
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wsr a2, EPC1 /* and store it back */
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apply_frame /* apply the results */
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rfe /* and done! */
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9:apply_frame /* restore the original registers */
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ret /* and hop back into the exception vector code */
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/* Our sneaky override of the UserExceptionVector to allow us to handle 8/16bit
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* loads from SPI flash. MUST be <= 32bytes compiled, as the next vector starts
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* there.
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*/
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.section ".UserExceptionVectorOverride.text"
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.type _UserExceptionVectorOverride,@function
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.globl _UserExceptionVectorOverride
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_UserExceptionVectorOverride:
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wsr a0, EXCSAVE1 /* free up a0 for a while */
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rsr a0, EXCCAUSE /* get the exception cause */
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bnei a0, 3, 2f /* if not EXCCAUSE_LOAD_STORE_ERROR, chain to rtos */
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j 1f /* jump past noncode bytes for cause3_handler addr */
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.align 4 /* proper alignment for literals */
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.literal_position /* the linker will put cause3_handler addr here */
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1:call0 cause3_handler /* handle loads with rfe, stores will return here */
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2:rsr a0, EXCSAVE1 /* restore a0 before we chain */
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j _UserExceptionVector /* and off we go to rtos */
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