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Explicitly set RMT config::flags. 

If this variable is not set in the config it may contain random data and set the clock source to the REF_CLK
resulting in timing errors, the DHTx, DS18B20 and ws2812 devices to not communicate.
This commit is contained in:
h2zero 2022-05-28 13:06:45 -06:00 committed by Johny Mattsson
parent 484a7721b5
commit b8ae6ca6f8
3 changed files with 4 additions and 0 deletions
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1
components/platform/dht.c
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@ -86,6 +86,7 @@ static int dht_init( uint8_t gpio_num )
rmt_rx.channel = dht_rmt.channel;
rmt_rx.gpio_num = gpio_num;
rmt_rx.clk_div = 80; // base period is 1us
rmt_rx.flags = 0;
rmt_rx.mem_block_num = 1;
rmt_rx.rmt_mode = RMT_MODE_RX;
rmt_rx.rx_config.filter_en = true;

2
components/platform/onewire.c
View File

@ -126,6 +126,7 @@ static int onewire_rmt_init( uint8_t gpio_num )
rmt_tx.gpio_num = gpio_num;
rmt_tx.mem_block_num = 1;
rmt_tx.clk_div = 80;
rmt_tx.flags = 0;
rmt_tx.tx_config.loop_en = false;
rmt_tx.tx_config.carrier_en = false;
rmt_tx.tx_config.idle_level = 1;
@ -138,6 +139,7 @@ static int onewire_rmt_init( uint8_t gpio_num )
rmt_rx.channel = ow_rmt.rx;
rmt_rx.gpio_num = gpio_num;
rmt_rx.clk_div = 80;
rmt_rx.flags = 0;
rmt_rx.mem_block_num = 1;
rmt_rx.rmt_mode = RMT_MODE_RX;
rmt_rx.rx_config.filter_en = true;

1
components/platform/ws2812.c
View File

@ -187,6 +187,7 @@ int platform_ws2812_send( void )
// common settings
rmt_tx.mem_block_num = 1;
rmt_tx.clk_div = WS2812_CLKDIV;
rmt_tx.flags = 0;
rmt_tx.tx_config.loop_en = false;
rmt_tx.tx_config.carrier_en = false;
rmt_tx.tx_config.idle_level = 0;