Initial version of code to support multiple hardware timers (#2497)
* Initial version of code to support multiple hardware timers * MAde the time sinca last tick work again * Add some documentation to the code
This commit is contained in:
Philip Gladstone
Marcel Stör
parent
dcc1ea2a49
commit
d75830407e
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@ -10,7 +10,7 @@
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#include "pin_map.h"
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#include "driver/gpio16.h"
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#define TIMER_OWNER 'P'
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#define TIMER_OWNER (('P' << 8) + 'U')
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#define xstr(s) str(s)
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#define str(s) #s
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@ -434,7 +434,7 @@ static int gpio_pulse_start(lua_State *L) {
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pulser->next_adjust = initial_adjust;
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// Now start things up
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if (!platform_hw_timer_init(TIMER_OWNER, FRC1_SOURCE, TRUE)) {
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if (!platform_hw_timer_init(TIMER_OWNER, FRC1_SOURCE, FALSE)) {
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// Failed to init the timer
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luaL_error(L, "Unable to initialize timer");
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}
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@ -7,21 +7,28 @@
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*
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* Modification history:
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* 2014/5/1, v1.0 create this file.
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*
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*
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* Adapted for NodeMCU 2016
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*
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*
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* The owner parameter should be a unique value per module using this API
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* It could be a pointer to a bit of data or code
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* e.g. #define OWNER ((os_param_t) module_init)
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* where module_init is a function. For builtin modules, it might be
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* It could be a pointer to a bit of data or code
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* e.g. #define OWNER ((os_param_t) module_init)
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* where module_init is a function. For builtin modules, it might be
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* a small numeric value that is known not to clash.
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*******************************************************************************/
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#include "platform.h"
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#include "c_stdio.h"
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#include "c_stdlib.h"
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#include "ets_sys.h"
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#include "os_type.h"
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#include "osapi.h"
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#include "hw_timer.h"
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//#define DEBUG_HW_TIMER
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//#undef NODE_DBG
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//#define NODE_DBG dbg_printf
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#define FRC1_ENABLE_TIMER BIT7
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#define FRC1_AUTO_LOAD BIT6
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@ -37,11 +44,227 @@ typedef enum { //timer interrupt mode
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TM_EDGE_INT = 0, //edge interrupt
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} TIMER_INT_MODE;
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static os_param_t the_owner;
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static os_param_t callback_arg;
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static void (* user_hw_timer_cb)(os_param_t);
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/*
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* This represents a single user of the timer functionality. It is keyed by the owner
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* field.
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*/
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typedef struct _timer_user {
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struct _timer_user *next;
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bool autoload;
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int32_t delay; // once on the active list, this is difference in delay from the preceding element
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int32_t autoload_delay;
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uint32_t expected_interrupt_time;
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os_param_t owner;
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os_param_t callback_arg;
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void (* user_hw_timer_cb)(os_param_t);
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#ifdef DEBUG_HW_TIMER
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int cb_count;
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#endif
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} timer_user;
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#define VERIFY_OWNER(owner) if (owner != the_owner) { if (the_owner) { return 0; } the_owner = owner; }
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/*
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* There are two lists of timer_user blocks. The active list are those which are waiting
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* for timeouts to happen, and the inactive list contains idle blocks. Unfortunately
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* there isn't a way to clean up the inactive blocks as some modules call the
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* close method from interrupt level.
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*/
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static timer_user *active;
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static timer_user *inactive;
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/*
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* There are a fair number of places when interrupts need to be disabled as many of
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* the methods can be called from interrupt level. The lock/unlock calls support
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* multiple LOCKs and then the same number of UNLOCKs are required to re-enable
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* interrupts. This is imolemeted by counting the number of times that lock is called.
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*/
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static uint8_t lock_count;
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static uint8_t timer_running;
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static uint32_t time_next_expiry;
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static int32_t last_timer_load;
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#define LOCK() do { ets_intr_lock(); lock_count++; } while (0)
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#define UNLOCK() if (--lock_count == 0) ets_intr_unlock()
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/*
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* To start a timer, you write to FRCI_LOAD_ADDRESS, and that starts the counting
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* down. When it reaches zero, the interrupt fires -- but the counting continues.
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* The counter is 23 bits wide. The current value of the counter can be read
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* at FRC1_COUNT_ADDRESS. The unit is 200ns, and so it takes somewhat over a second
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* to wrap the counter.
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*/
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#ifdef DEBUG_HW_TIMER
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void ICACHE_RAM_ATTR hw_timer_debug() {
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dbg_printf("timer_running=%d\n", timer_running);
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timer_user *tu;
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for (tu = active; tu; tu = tu->next) {
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dbg_printf("Owner: 0x%x, delay=%d, autoload=%d, autoload_delay=%d, cb_count=%d\n",
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tu->owner, tu->delay, tu->autoload, tu->autoload_delay, tu->cb_count);
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}
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}
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#endif
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static void ICACHE_RAM_ATTR set_timer(int delay, const char *caller) {
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if (delay < 1) {
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delay = 1;
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}
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int32_t time_left = (RTC_REG_READ(FRC1_COUNT_ADDRESS)) & ((1 << 23) - 1);
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RTC_REG_WRITE(FRC1_LOAD_ADDRESS, delay);
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if (time_left > last_timer_load) {
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// We have missed the interrupt
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time_left -= 1 << 23;
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}
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NODE_DBG("%s(%x): time_next=%d, left=%d (load=%d), delay=%d => %d\n", caller, active->owner, time_next_expiry, time_left, last_timer_load, delay, time_next_expiry - time_left + delay);
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time_next_expiry = time_next_expiry - time_left + delay;
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last_timer_load = delay;
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timer_running = 1;
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}
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static void ICACHE_RAM_ATTR adjust_root() {
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// Can only ge called with interrupts disabled
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// change the initial active delay so that relative stuff still works
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// Also, set the last_timer_load to be now
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int32_t time_left = (RTC_REG_READ(FRC1_COUNT_ADDRESS)) & ((1 << 23) - 1);
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if (time_left > last_timer_load) {
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// We have missed the interrupt
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time_left -= 1 << 23;
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}
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if (active && timer_running) {
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active->delay = time_left;
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}
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if (active) {
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NODE_DBG("adjust(%x): time_left=%d (last_load=%d)\n", active->owner, time_left, last_timer_load);
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} else {
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NODE_DBG("adjust: time_left=%d (last_load=%d)\n", time_left, last_timer_load);
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}
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last_timer_load = time_left;
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}
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/*
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* Find the timer_user block for this owner. This just returns
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* a pointer to the block, or NULL.
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*/
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static timer_user * ICACHE_RAM_ATTR find_tu(os_param_t owner) {
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// Try the inactive chain first
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timer_user **p;
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LOCK();
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for (p = &inactive; *p; p = &((*p)->next)) {
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if ((*p)->owner == owner) {
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timer_user *result = *p;
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UNLOCK();
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return result;
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}
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}
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for (p = &active; *p; p = &((*p)->next)) {
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if ((*p)->owner == owner) {
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timer_user *result = *p;
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UNLOCK();
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return result;
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}
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}
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UNLOCK();
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return NULL;
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}
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/*
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* Find the timer_user block for this owner. This just returns
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* a pointer to the block, or NULL. If it finds the block, then it is
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* removed from whichever chain it is on. Note that this may require
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* triggering a timer.
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*/
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static timer_user * ICACHE_RAM_ATTR find_tu_and_remove(os_param_t owner) {
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// Try the inactive chain first
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timer_user **p;
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LOCK();
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for (p = &inactive; *p; p = &((*p)->next)) {
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if ((*p)->owner == owner) {
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timer_user *result = *p;
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*p = result->next;
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result->next = NULL;
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UNLOCK();
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return result;
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}
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}
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for (p = &active; *p; p = &((*p)->next)) {
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if ((*p)->owner == owner) {
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timer_user *result = *p;
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bool need_to_reset = (result == active) && result->next;
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if (need_to_reset) {
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adjust_root();
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}
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// Increase the delay on the next element
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if (result->next) {
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result->next->delay += result->delay;
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}
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// Cut out of chain
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*p = result->next;
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result->next = NULL;
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if (need_to_reset) {
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set_timer(active->delay, "find_tu");
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}
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UNLOCK();
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return result;
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}
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}
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UNLOCK();
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return NULL;
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}
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/*
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* This inserts a timer_user block into the active chain. This is a sightly
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* complex process as it can involve triggering a timer load.
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*/
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static void ICACHE_RAM_ATTR insert_active_tu(timer_user *tu) {
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timer_user **p;
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LOCK();
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tu->expected_interrupt_time = time_next_expiry - last_timer_load + tu->delay;
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for (p = &active; *p; p = &((*p)->next)) {
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if ((*p)->delay >= tu->delay) {
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break;
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}
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tu->delay -= (*p)->delay;
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}
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if (*p) {
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(*p)->delay -= tu->delay;
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}
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tu->next = *p;
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*p = tu;
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if (tu == active) {
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// We have a new leader
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set_timer(active->delay, "insert_active");
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}
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UNLOCK();
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}
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/******************************************************************************
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* FunctionName : platform_hw_timer_arm_ticks
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@ -52,10 +275,23 @@ static void (* user_hw_timer_cb)(os_param_t);
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*******************************************************************************/
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bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks(os_param_t owner, uint32_t ticks)
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{
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VERIFY_OWNER(owner);
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RTC_REG_WRITE(FRC1_LOAD_ADDRESS, ticks);
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timer_user *tu = find_tu_and_remove(owner);
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return 1;
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if (!tu) {
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return false;
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}
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tu->delay = ticks;
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tu->autoload_delay = ticks;
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NODE_DBG("arm(%x): ticks=%d\n", owner, ticks);
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LOCK();
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adjust_root();
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insert_active_tu(tu);
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UNLOCK();
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return true;
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}
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/******************************************************************************
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@ -72,10 +308,7 @@ bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks(os_param_t owner, uint32_t tick
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*******************************************************************************/
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bool ICACHE_RAM_ATTR platform_hw_timer_arm_us(os_param_t owner, uint32_t microseconds)
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{
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VERIFY_OWNER(owner);
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RTC_REG_WRITE(FRC1_LOAD_ADDRESS, US_TO_RTC_TIMER_TICKS(microseconds));
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return 1;
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return platform_hw_timer_arm_ticks(owner, US_TO_RTC_TIMER_TICKS(microseconds));
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}
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/******************************************************************************
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@ -89,24 +322,67 @@ bool ICACHE_RAM_ATTR platform_hw_timer_arm_us(os_param_t owner, uint32_t microse
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*******************************************************************************/
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bool platform_hw_timer_set_func(os_param_t owner, void (* user_hw_timer_cb_set)(os_param_t), os_param_t arg)
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{
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VERIFY_OWNER(owner);
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callback_arg = arg;
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user_hw_timer_cb = user_hw_timer_cb_set;
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return 1;
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timer_user *tu = find_tu(owner);
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if (!tu) {
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return false;
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}
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tu->callback_arg = arg;
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tu->user_hw_timer_cb = user_hw_timer_cb_set;
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NODE_DBG("set-CB(%x): %x, %x\n", tu->owner, tu->user_hw_timer_cb, tu->callback_arg);
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return true;
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}
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/*
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* This is the timer ISR. It has to find the timer that was running and trigger the callback
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* for that timer. By this stage, the next timer may have expired as well, and so the process
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* iterates. Note that if there is an autoload timer, then it should be restarted immediately.
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* Also, the callbacks typically do re-arm the timer, so we have to be careful not to
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* assume that nothing changes during the callback.
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*/
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static void ICACHE_RAM_ATTR hw_timer_isr_cb(void *arg)
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{
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if (user_hw_timer_cb != NULL) {
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(*(user_hw_timer_cb))(callback_arg);
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bool keep_going = true;
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adjust_root();
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timer_running = 0;
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while (keep_going && active) {
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keep_going = false;
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timer_user *fired = active;
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active = fired->next;
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if (fired->autoload) {
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fired->expected_interrupt_time += fired->autoload_delay;
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fired->delay = fired->expected_interrupt_time - (time_next_expiry - last_timer_load);
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insert_active_tu(fired);
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if (active->delay <= 0) {
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keep_going = true;
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}
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} else {
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fired->next = inactive;
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inactive = fired;
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if (active) {
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active->delay += fired->delay;
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if (active->delay <= 0) {
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keep_going = true;
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}
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}
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}
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if (fired->user_hw_timer_cb) {
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#ifdef DEBUG_HW_TIMER
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fired->cb_count++;
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#endif
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NODE_DBG("CB(%x): %x, %x\n", fired->owner, fired->user_hw_timer_cb, fired->callback_arg);
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(*(fired->user_hw_timer_cb))(fired->callback_arg);
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}
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}
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if (active && !timer_running) {
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set_timer(active->delay, "isr");
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}
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}
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static void ICACHE_RAM_ATTR hw_timer_nmi_cb(void)
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{
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if (user_hw_timer_cb != NULL) {
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(*(user_hw_timer_cb))(callback_arg);
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}
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hw_timer_isr_cb(NULL);
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}
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/******************************************************************************
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@ -117,9 +393,21 @@ static void ICACHE_RAM_ATTR hw_timer_nmi_cb(void)
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*******************************************************************************/
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uint32_t ICACHE_RAM_ATTR platform_hw_timer_get_delay_ticks(os_param_t owner)
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{
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VERIFY_OWNER(owner);
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timer_user *tu = find_tu(owner);
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if (!tu) {
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return 0;
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}
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return (- RTC_REG_READ(FRC1_COUNT_ADDRESS)) & ((1 << 23) - 1);
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LOCK();
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adjust_root();
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UNLOCK();
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int ret = (time_next_expiry - last_timer_load) - tu->expected_interrupt_time;
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if (ret < 0) {
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NODE_DBG("delay ticks = %d, last_timer_load=%d, tu->expected_int=%d, next_exp=%d\n", ret, last_timer_load, tu->expected_interrupt_time, time_next_expiry);
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}
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return ret < 0 ? 0 : ret;
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}
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/******************************************************************************
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@ -136,25 +424,34 @@ uint32_t ICACHE_RAM_ATTR platform_hw_timer_get_delay_ticks(os_param_t owner)
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*******************************************************************************/
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bool platform_hw_timer_init(os_param_t owner, FRC1_TIMER_SOURCE_TYPE source_type, bool autoload)
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{
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VERIFY_OWNER(owner);
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if (autoload) {
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RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
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FRC1_AUTO_LOAD | DIVIDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
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} else {
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timer_user *tu = find_tu_and_remove(owner);
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if (!tu) {
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tu = (timer_user *) c_malloc(sizeof(*tu));
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if (!tu) {
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return false;
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}
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memset(tu, 0, sizeof(*tu));
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tu->owner = owner;
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}
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tu->autoload = autoload;
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if (!active && !inactive) {
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RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
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DIVIDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
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}
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if (source_type == NMI_SOURCE) {
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ETS_FRC_TIMER1_NMI_INTR_ATTACH(hw_timer_nmi_cb);
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} else {
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ETS_FRC_TIMER1_INTR_ATTACH(hw_timer_isr_cb, NULL);
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TM1_EDGE_INT_ENABLE();
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ETS_FRC1_INTR_ENABLE();
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}
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TM1_EDGE_INT_ENABLE();
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ETS_FRC1_INTR_ENABLE();
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LOCK();
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tu->next = inactive;
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inactive = tu;
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UNLOCK();
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return 1;
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return true;
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}
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/******************************************************************************
|
||||
|
|
@ -165,19 +462,25 @@ bool platform_hw_timer_init(os_param_t owner, FRC1_TIMER_SOURCE_TYPE source_type
|
|||
*******************************************************************************/
|
||||
bool ICACHE_RAM_ATTR platform_hw_timer_close(os_param_t owner)
|
||||
{
|
||||
VERIFY_OWNER(owner);
|
||||
timer_user *tu = find_tu_and_remove(owner);
|
||||
|
||||
/* Set no reload mode */
|
||||
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
|
||||
DIVIDED_BY_16 | TM_EDGE_INT);
|
||||
if (tu) {
|
||||
LOCK();
|
||||
tu->next = inactive;
|
||||
inactive = tu;
|
||||
UNLOCK();
|
||||
}
|
||||
|
||||
TM1_EDGE_INT_DISABLE();
|
||||
ETS_FRC1_INTR_DISABLE();
|
||||
// This will never actually run....
|
||||
if (!active && !inactive) {
|
||||
/* Set no reload mode */
|
||||
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
|
||||
DIVIDED_BY_16 | TM_EDGE_INT);
|
||||
|
||||
user_hw_timer_cb = NULL;
|
||||
TM1_EDGE_INT_DISABLE();
|
||||
ETS_FRC1_INTR_DISABLE();
|
||||
}
|
||||
|
||||
the_owner = 0;
|
||||
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue