rework parts of I2S
This commit is contained in:
devsaurus
parent
5e64def682
commit
daa5848431
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@ -1,5 +1,7 @@
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// Module for interfacing with i2s hardware
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#include <string.h>
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#include "module.h"
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#include "lauxlib.h"
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#include "lmem.h"
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@ -19,106 +21,211 @@
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#define I2S_CHECK_ID(id) if(id >= MAX_I2C_NUM) luaL_error( L, "i2s not exists" )
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typedef struct {
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xTaskHandle taskHandle;
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QueueHandle_t *event_queue;
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int event_cb;
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} i2s_status_t;
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int ref;
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const char *data;
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size_t len;
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} i2s_tx_data_t;
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typedef struct {
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i2s_event_t event;
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i2s_status_t* status;
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} i2s_event_post_type;
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struct {
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xTaskHandle taskHandle;
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QueueHandle_t queue;
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} tx;
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struct {
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xTaskHandle taskHandle;
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QueueHandle_t queue;
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} rx;
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int cb;
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int i2s_bits_per_sample, data_bits_per_sample;
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} i2s_status_t;
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static task_handle_t i2s_event_task_id;
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static task_handle_t i2s_tx_task_id, i2s_rx_task_id, i2s_disposal_task_id;
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static i2s_status_t i2s_status[MAX_I2C_NUM];
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// LUA
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static void i2s_event_task( task_param_t param, task_prio_t prio ) {
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i2s_event_post_type *post = (i2s_event_post_type *)param;
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static void i2s_tx_task( task_param_t param, task_prio_t prio ) {
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int i2s_id = (int)param;
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i2s_status_t *is = &i2s_status[i2s_id];
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if (is->cb != LUA_NOREF) {
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lua_State *L = lua_getstate();
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int event_cb = post->status->event_cb;
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if(event_cb == LUA_NOREF) {
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free( post );
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return;
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}
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lua_rawgeti(L, LUA_REGISTRYINDEX, event_cb);
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if(post->event.type == I2S_EVENT_TX_DONE)
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lua_pushstring(L, "sent");
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else if(post->event.type == I2S_EVENT_RX_DONE)
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lua_pushstring(L, "data");
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else
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lua_pushstring(L, "error");
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lua_pushinteger(L, post->event.size);
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free( post );
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lua_rawgeti(L, LUA_REGISTRYINDEX, is->cb);
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lua_pushinteger( L, i2s_id );
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lua_pushstring( L, "tx" );
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lua_call( L, 2, 0 );
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}
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}
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static void i2s_rx_task( task_param_t param, task_prio_t prio ) {
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int i2s_id = (int)param;
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i2s_status_t *is = &i2s_status[i2s_id];
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if (is->cb != LUA_NOREF) {
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lua_State *L = lua_getstate();
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lua_rawgeti(L, LUA_REGISTRYINDEX, is->cb);
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lua_pushinteger( L, i2s_id );
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lua_pushstring( L, "rx" );
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lua_call( L, 2, 0 );
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}
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}
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static void i2s_disposal_task( task_param_t param, task_prio_t prio ) {
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lua_State *L = lua_getstate();
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int ref = (int)param;
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luaL_unref( L, LUA_REGISTRYINDEX, ref );
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}
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// RTOS
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static void task_I2S( void *pvParameters ){
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i2s_status_t* is = (i2s_status_t*)pvParameters;
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static void task_I2S_rx( void *pvParameters ) {
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int i2s_id = (int)pvParameters;
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i2s_status_t *is = &i2s_status[i2s_id];
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i2s_event_t event;
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i2s_event_t i2s_event;
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for (;;) {
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if( xQueueReceive( is->event_queue, &event, 3 * portTICK_PERIOD_MS ) == pdTRUE ){
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i2s_event_post_type *post = (i2s_event_post_type *)malloc( sizeof( i2s_event_post_type ) );
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post->status = is;
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memcpy(&(post->event), &event, sizeof(i2s_event_t));
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task_post_high( i2s_event_task_id, (task_param_t)post );
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// process I2S RX events
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xQueueReceive( is->rx.queue, &i2s_event, portMAX_DELAY );
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if (i2s_event.type == I2S_EVENT_RX_DONE) {
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task_post_high( i2s_rx_task_id, i2s_id );
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}
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}
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}
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static void task_I2S_tx( void *pvParameters ) {
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int i2s_id = (int)pvParameters;
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i2s_status_t *is = &i2s_status[i2s_id];
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i2s_tx_data_t tx_data;
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for (;;) {
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// request new TX data
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task_post_high( i2s_tx_task_id, i2s_id );
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// get TX data from Lua task
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xQueueReceive( is->tx.queue, &tx_data, portMAX_DELAY );
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// write TX data to I2S, note that this call might block
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size_t dummy;
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if (is->data_bits_per_sample == is->i2s_bits_per_sample) {
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i2s_write( i2s_id, tx_data.data, tx_data.len, &dummy, portMAX_DELAY );
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} else {
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i2s_write_expand( i2s_id, tx_data.data, tx_data.len, is->data_bits_per_sample, is->i2s_bits_per_sample, &dummy, portMAX_DELAY );
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}
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// notify Lua to dispose object
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task_post_low( i2s_disposal_task_id, tx_data.ref );
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}
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}
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// Lua: start( i2s_id, {}, callback )
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static int node_i2s_start( lua_State *L )
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{
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int i2s_id = luaL_checkinteger( L, 1 );
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I2S_CHECK_ID( i2s_id );
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i2s_status_t *is = &i2s_status[i2s_id];
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int top = lua_gettop( L );
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luaL_checkanytable (L, 2);
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i2s_config_t i2s_config;
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memset( &i2s_config, 0, sizeof( i2s_config ) );
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i2s_pin_config_t pin_config;
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memset( &pin_config, 0, sizeof( pin_config ) );
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lua_getfield (L, 2, "mode");
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i2s_config.mode = luaL_optint(L, -1, I2S_MODE_MASTER | I2S_MODE_TX);
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//
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lua_getfield (L, 2, "rate");
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i2s_config.sample_rate = luaL_optint(L, -1, 44100);
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//
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lua_getfield (L, 2, "bits");
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i2s_config.bits_per_sample = 16;
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is->data_bits_per_sample = luaL_optint(L, -1, 16);
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is->i2s_bits_per_sample = is->data_bits_per_sample < I2S_BITS_PER_SAMPLE_16BIT ? I2S_BITS_PER_SAMPLE_16BIT : is->data_bits_per_sample;
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i2s_config.bits_per_sample = is->i2s_bits_per_sample;
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//
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lua_getfield (L, 2, "channel");
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i2s_config.channel_format = luaL_optint(L, -1, I2S_CHANNEL_FMT_RIGHT_LEFT);
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//
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lua_getfield (L, 2, "format");
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i2s_config.communication_format = luaL_optint(L, -1, I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB);
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//
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lua_getfield (L, 2, "buffer_count");
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i2s_config.dma_buf_count = luaL_optint(L, -1, 2);
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//
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lua_getfield (L, 2, "buffer_len");
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i2s_config.dma_buf_len = luaL_optint(L, -1, i2s_config.sample_rate / 100);
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i2s_config.intr_alloc_flags = ESP_INTR_FLAG_LEVEL2;
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//
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i2s_config.intr_alloc_flags = ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_IRAM;
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//
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lua_getfield (L, 2, "bck_pin");
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pin_config.bck_io_num = luaL_optint(L, -1, I2S_PIN_NO_CHANGE);
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//
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lua_getfield (L, 2, "ws_pin");
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pin_config.ws_io_num = luaL_optint(L, -1, I2S_PIN_NO_CHANGE);
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//
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lua_getfield (L, 2, "data_out_pin");
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pin_config.data_out_num = luaL_optint(L, -1, I2S_PIN_NO_CHANGE);
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//
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lua_getfield (L, 2, "data_in_pin");
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pin_config.data_in_num = luaL_optint(L, -1, I2S_PIN_NO_CHANGE);
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//
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lua_getfield(L, 2, "dac_mode");
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i2s_dac_mode_t dac_mode = luaL_optint(L, -1, I2S_DAC_CHANNEL_DISABLE);
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//
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lua_getfield(L, 2, "adc1_channel");
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adc1_channel_t adc1_channel = luaL_optint(L, -1, ADC1_CHANNEL_MAX);
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lua_settop(L, 3);
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i2s_status[i2s_id].event_cb = luaL_ref(L, LUA_REGISTRYINDEX);
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// handle optional callback functions TX and RX
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lua_settop( L, top );
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if (lua_isfunction( L, 3 )) {
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lua_pushvalue( L, 3 );
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is->cb = luaL_ref( L, LUA_REGISTRYINDEX );
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} else {
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is->cb = LUA_NOREF;
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}
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esp_err_t err = i2s_driver_install(i2s_id, &i2s_config, i2s_config.dma_buf_count, &i2s_status[i2s_id].event_queue);
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esp_err_t err;
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if (i2s_config.mode & I2S_MODE_RX) {
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err = i2s_driver_install(i2s_id, &i2s_config, i2s_config.dma_buf_count, &is->rx.queue);
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} else {
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err = i2s_driver_install(i2s_id, &i2s_config, i2s_config.dma_buf_count, NULL);
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}
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if (err != ESP_OK)
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luaL_error( L, "i2s can not start" );
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i2s_set_pin(i2s_id, &pin_config);
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char pcName[5];
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snprintf( pcName, 5, "I2S%d", i2s_id );
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pcName[4] = '\0';
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xTaskCreate(task_I2S, pcName, 2048, &i2s_status[i2s_id], ESP_TASK_MAIN_PRIO + 1, &i2s_status[i2s_id].taskHandle);
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if (dac_mode != I2S_DAC_CHANNEL_DISABLE) {
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if (i2s_set_dac_mode( dac_mode ) != ESP_OK)
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luaL_error( L, "error setting dac mode" );
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}
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if (adc1_channel != ADC1_CHANNEL_MAX) {
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if (i2s_set_adc_mode( ADC_UNIT_1, adc1_channel ) != ESP_OK)
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luaL_error( L, "error setting adc1 mode" );
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}
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if (i2s_set_pin(i2s_id, &pin_config) != ESP_OK)
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luaL_error( L, "error setting pins" );
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if (i2s_config.mode & I2S_MODE_TX) {
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// prepare TX task
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char pcName[8];
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snprintf( pcName, 8, "I2S_tx_%d", i2s_id );
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pcName[7] = '\0';
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if ((is->tx.queue = xQueueCreate( 2, sizeof( i2s_tx_data_t ) )) == NULL)
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return luaL_error( L, "cannot create queue" );
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xTaskCreate(task_I2S_tx, pcName, 2048, (void *)i2s_id, ESP_TASK_MAIN_PRIO + 1, &is->tx.taskHandle);
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}
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if (i2s_config.mode & I2S_MODE_RX) {
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// prepare RX task
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char pcName[8];
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snprintf( pcName, 8, "I2S_rx_%d", i2s_id );
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pcName[7] = '\0';
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xTaskCreate(task_I2S_rx, pcName, 1024, (void *)i2s_id, ESP_TASK_MAIN_PRIO + 1, &is->rx.taskHandle);
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}
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return 0;
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}
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@ -128,18 +235,28 @@ static int node_i2s_stop( lua_State *L )
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{
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int i2s_id = luaL_checkinteger( L, 1 );
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I2S_CHECK_ID( i2s_id );
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i2s_status_t *is = &i2s_status[i2s_id];
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i2s_driver_uninstall(i2s_id);
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i2s_status[i2s_id].event_queue = NULL;
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if(i2s_status[i2s_id].taskHandle != NULL) {
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vTaskDelete(i2s_status[i2s_id].taskHandle);
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i2s_status[i2s_id].taskHandle = NULL;
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if (is->tx.taskHandle != NULL) {
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vTaskDelete( is->tx.taskHandle );
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is->tx.taskHandle = NULL;
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}
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if (is->tx.queue != NULL) {
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vQueueDelete( is->tx.queue );
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is->tx.queue = NULL;
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}
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if(i2s_status[i2s_id].event_cb != LUA_NOREF) {
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luaL_unref(L, LUA_REGISTRYINDEX, i2s_status[i2s_id].event_cb);
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i2s_status[i2s_id].event_cb = LUA_NOREF;
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if (is->rx.taskHandle != NULL) {
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vTaskDelete( is->rx.taskHandle );
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is->rx.taskHandle = NULL;
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}
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// the rx queue is created and destroyed by the I2S driver
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if (is->cb != LUA_NOREF) {
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luaL_unref( L, LUA_REGISTRYINDEX, is->cb );
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is->cb = LUA_NOREF;
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}
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return 0;
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@ -152,40 +269,33 @@ static int node_i2s_read( lua_State *L )
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I2S_CHECK_ID( i2s_id );
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size_t bytes = luaL_checkinteger( L, 2 );
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int wait_ms = luaL_optint(L, 3, 0);
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//int wait_ms = luaL_optint(L, 3, 0);
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char * data = luaM_malloc( L, bytes );
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size_t read = i2s_read_bytes(i2s_id, data, bytes, wait_ms / portTICK_RATE_MS);
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size_t read = 0;
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//read = i2s_read_bytes(i2s_id, data, bytes, wait_ms / portTICK_RATE_MS);
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lua_pushlstring(L, data, read);
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luaM_free(L, data);
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return 1;
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}
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// Lua: write( i2s_id, data[, wait_ms] )
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// Lua: write( i2s_id, data )
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static int node_i2s_write( lua_State *L )
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{
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int i2s_id = luaL_checkinteger( L, 1 );
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int stack = 0;
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int i2s_id = luaL_checkinteger( L, ++stack );
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I2S_CHECK_ID( i2s_id );
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size_t bytes;
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char *data;
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if( lua_istable( L, 2 ) ) {
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bytes = lua_objlen( L, 2 );
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data = (char *)luaM_malloc( L, bytes );
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for( int i = 0; i < bytes; i ++ ) {
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lua_rawgeti( L, 2, i + 1 );
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data[i] = (uint8_t)luaL_checkinteger( L, -1 );
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}
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} else {
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data = (char *) luaL_checklstring(L, 2, &bytes);
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}
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int wait_ms = luaL_optint(L, 3, 0);
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size_t wrote = i2s_write_bytes(i2s_id, data, bytes, wait_ms / portTICK_RATE_MS);
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if( lua_istable( L, 2 ) )
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luaM_free(L, data);
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lua_pushinteger( L, ( lua_Integer ) wrote );
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i2s_tx_data_t tx_data;
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tx_data.data = (const char *)luaL_checklstring( L, ++stack, &tx_data.len );
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lua_pushvalue( L, stack );
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tx_data.ref = luaL_ref( L, LUA_REGISTRYINDEX );
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return 1;
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// post this to the TX task
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xQueueSendToBack( i2s_status[i2s_id].tx.queue, &tx_data, portMAX_DELAY );
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return 0;
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}
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// Module function map
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@ -195,6 +305,7 @@ static const LUA_REG_TYPE i2s_map[] =
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{ LSTRKEY( "stop" ), LFUNCVAL( node_i2s_stop ) },
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{ LSTRKEY( "read" ), LFUNCVAL( node_i2s_read ) },
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{ LSTRKEY( "write" ), LFUNCVAL( node_i2s_write ) },
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{ LSTRKEY( "FORMAT_I2S" ), LNUMVAL( I2S_COMM_FORMAT_I2S ) },
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{ LSTRKEY( "FORMAT_I2S_MSB" ), LNUMVAL( I2S_COMM_FORMAT_I2S_MSB ) },
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{ LSTRKEY( "FORMAT_I2S_LSB" ), LNUMVAL( I2S_COMM_FORMAT_I2S_LSB ) },
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@ -213,17 +324,29 @@ static const LUA_REG_TYPE i2s_map[] =
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{ LSTRKEY( "MODE_TX" ), LNUMVAL( I2S_MODE_TX ) },
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{ LSTRKEY( "MODE_RX" ), LNUMVAL( I2S_MODE_RX ) },
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{ LSTRKEY( "MODE_DAC_BUILT_IN" ), LNUMVAL( I2S_MODE_DAC_BUILT_IN ) },
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{ LSTRKEY( "MODE_ADC_BUILT_IN" ), LNUMVAL( I2S_MODE_ADC_BUILT_IN ) },
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{ LSTRKEY( "MODE_PDM" ), LNUMVAL( I2S_MODE_PDM ) },
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{ LSTRKEY( "DAC_CHANNEL_DISABLE" ), LNUMVAL( I2S_DAC_CHANNEL_DISABLE ) },
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{ LSTRKEY( "DAC_CHANNEL_RIGHT" ), LNUMVAL( I2S_DAC_CHANNEL_RIGHT_EN ) },
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{ LSTRKEY( "DAC_CHANNEL_LEFT" ), LNUMVAL( I2S_DAC_CHANNEL_LEFT_EN ) },
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{ LSTRKEY( "DAC_CHANNEL_BOTH" ), LNUMVAL( I2S_DAC_CHANNEL_BOTH_EN ) },
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{ LNILKEY, LNILVAL }
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};
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|
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int luaopen_i2s( lua_State *L ) {
|
||||
for(int i2s_id = 0; i2s_id < MAX_I2C_NUM; i2s_id++) {
|
||||
i2s_status[i2s_id].event_queue = NULL;
|
||||
i2s_status[i2s_id].taskHandle = NULL;
|
||||
i2s_status[i2s_id].event_cb = LUA_NOREF;
|
||||
i2s_status_t *is = &i2s_status[i2s_id];
|
||||
is->tx.queue = NULL;
|
||||
is->tx.taskHandle = NULL;
|
||||
is->rx.queue = NULL;
|
||||
is->rx.taskHandle = NULL;
|
||||
is->cb = LUA_NOREF;
|
||||
}
|
||||
i2s_event_task_id = task_get_id( i2s_event_task );
|
||||
i2s_tx_task_id = task_get_id( i2s_tx_task );
|
||||
i2s_rx_task_id = task_get_id( i2s_rx_task );
|
||||
i2s_disposal_task_id = task_get_id( i2s_disposal_task );
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,57 +1,71 @@
|
|||
# I2S Module
|
||||
| Since | Origin / Contributor | Maintainer | Source |
|
||||
| :----- | :-------------------- | :---------- | :------ |
|
||||
| 2017-04-29 | zelll | | [i2s.c](../../../components/modules/i2s.c)|
|
||||
| 2017-04-29 | zelll | [Arnim Läuger](https://github.com/devsaurus) | [i2s.c](../../../components/modules/i2s.c)|
|
||||
|
||||
The I2S module provides access to the in-built two I2S controllers.
|
||||
|
||||
!!! note "DAC mode configuration"
|
||||
DACs are only available for DAC built-in mode on I2S peripheral 0.
|
||||
|
||||
!!! note "ADC mode configuration"
|
||||
Only ADC1 is available for ADC built-in mode.
|
||||
|
||||
## i2s.start()
|
||||
Configuration and start I2S bus.
|
||||
|
||||
#### Syntax
|
||||
```lua
|
||||
i2s.start(i2s_num, cfg = {
|
||||
mode = can.MODE_MASTER + can.MODE_TX,
|
||||
rate = 44100,
|
||||
bits = 16,
|
||||
channel = i2s.CHANNEL_RIGHT_LEFT,
|
||||
format = i2s.FORMAT_I2S + i2s.FORMAT_I2S_MSB,
|
||||
buffer_count = 2,
|
||||
buffer_len = 441,
|
||||
bck_pin = 16,
|
||||
ws_pin = 17,
|
||||
data_out_pin = 18,
|
||||
data_in_pin = -1
|
||||
}, callback)
|
||||
i2s.start(i2s_num, cfg, cb)
|
||||
```
|
||||
|
||||
#### Parameters
|
||||
- `i2s_num` `1` or `2`
|
||||
- `cfg` configuration
|
||||
- `mode` combine of following constants `i2s.MODE_MASTER`, `i2s.MODE_SLAVE`, `i2s.MODE_TX`, `i2s.MODE_RX`, `i2s.MODE_DAC_BUILT_IN`. Default: `i2s.MODE_MASTER + i2s.MODE_TX`
|
||||
- `rate` Audio sample rate, such as `44100`, `48000`, `16000`, `800`. Default: `44100`
|
||||
- `bits` `32`, `24`, `16` or `8`. Default: `16`
|
||||
- `channel` One of following constants. Default: `i2s.CHANNEL_RIGHT_LEFT`
|
||||
- `i2s_num` I2S peripheral 0 or 1
|
||||
- `cfg` table containing configuration data:
|
||||
- `mode` I2S work mode. Optional, defaults to `i2s.MODE_MASTER + i2s.MODE_TX` when omitted
|
||||
- `i2s.MODE_MASTER`
|
||||
- `i2s.MODE_SLAVE`
|
||||
- `i2s.MODE_TX`
|
||||
- `i2s.MODE_RX`
|
||||
- `i2s.MODE_DAC_BUILT_IN`
|
||||
- `i2s.MODE_ADC_BUILT_IN`
|
||||
- `i2s.MODE_PDM`
|
||||
- `rate` audio sample rate. Optional, defauls to 44100 when omitted
|
||||
- `bits` bits per sample. Optional, defaults to 16 when omitted
|
||||
- `channel` channel format of I2S stream. Optional, defaults to `i2s.CHANNEL_RIGHT_LEFT` when omitted
|
||||
- `i2s.CHANNEL_RIGHT_LEFT`
|
||||
- `i2s.CHANNEL_ALL_LEFT`
|
||||
- `i2s.CHANNEL_ONLY_LEFT`
|
||||
- `i2s.CHANNEL_ALL_RIGHT`
|
||||
- `i2s.CHANNEL_ONLY_RIGHT`
|
||||
- `format` combine of following constants `i2s.FORMAT_I2S`, `i2s.FORMAT_I2S_MSB`, `i2s.FORMAT_I2S_LSB`, `i2s.FORMAT_PCM`, `i2s.FORMAT_PCM_SHORT`, `i2s.FORMAT_PCM_LONG`.
|
||||
Default: `i2s.FORMAT_I2S + i2s.FORMAT_I2S_MSB`
|
||||
- `buffer_count` Buffer count. Default: 2
|
||||
- `buffer_len` Size of one buffer. Default: rate/100
|
||||
- `bck_pin` Clock pin. Default: `-1`
|
||||
- `ws_pin` WS pin. Default: `-1`
|
||||
- `data_out_pin` Pin for data output. Default: `-1`
|
||||
- `data_in_pin` Pin for data input. Default: `-1`
|
||||
- `callback` function called when i2s event occurs.
|
||||
- `event` Event type, one of `sent`, `data`, `error`
|
||||
- `size` bytes
|
||||
- `format` communicarion format. Optional, defaults to `i2s.FORMAT_I2S + i2s.FORMAT_I2S_MSB` when omitted
|
||||
- `i2s.FORMAT_I2S`
|
||||
- `i2s.FORMAT_I2S_MSB`
|
||||
- `i2s.FORMAT_I2S_LSB`
|
||||
- `i2s.FORMAT_PCM`
|
||||
- `i2s.FORMAT_PCM_SHORT`
|
||||
- `i2s.FORMAT_PCM_LONG`
|
||||
- `buffer_count` number of dma buffers. Optional, defaults to 2 when omitted
|
||||
- `buffer_len` size of one dma buffer. Optional, defaults to rate/100
|
||||
- `bck_pin` clock pin, optional
|
||||
- `ws_pin` WS pin, optional
|
||||
- `data_out_pin` data output pin, optional
|
||||
- `data_in_pin` data input pin, optional
|
||||
- `dac_mode` DAC mode configuration. Optional, defaults to `i2s.DAC_CHANNEL_DISABLE` if omitted
|
||||
- `i2s.DAC_CHANNEL_DISABLE`
|
||||
- `i2s.DAC_CHANNEL_RIGHT`
|
||||
- `i2s.DAC_CHANNEL_LEFT`
|
||||
- `i2s.DAC_CHANNEL_BOTH`
|
||||
- `adc1_channel` ADC1 channel number 0..7. Optional, defaults to off is omitted
|
||||
- `cb` function called when transmit data is requested or received data is available
|
||||
- the function is called with parameters `i2s_num` and `dir`
|
||||
- `dir` is "tx" for TX data request. Function shall call `i2s.write()`.
|
||||
- `dir` is "rx" for RX data available. Function shall call `i2s.read()`.
|
||||
|
||||
#### Returns
|
||||
nil
|
||||
`nil`
|
||||
|
||||
An error is thrown in case of invalid parameters or if the channel failed.
|
||||
|
||||
|
||||
## i2s.stop()
|
||||
|
|
@ -61,10 +75,12 @@ Stop I2S bus
|
|||
`i2s.stop(i2s_num)`
|
||||
|
||||
#### Parameters
|
||||
- `i2s_num` `1` or `2`
|
||||
- `i2s_num` I2S peripheral 0 or 1
|
||||
|
||||
#### Returns
|
||||
nil
|
||||
`nil`
|
||||
|
||||
An error is thrown in case of invalid parameters or if the channel failed.
|
||||
|
||||
|
||||
## i2s.read()
|
||||
|
|
@ -74,24 +90,25 @@ Read data from data-in
|
|||
`i2s.read(i2s_num, size[, wait_ms])`
|
||||
|
||||
#### Parameters
|
||||
- `adc_number` Only `adc.ADC1` now
|
||||
- `i2s_num` I2S peripheral 0 or 1
|
||||
- `size` Bytes to read
|
||||
- `wait_ms` Millisecond to wait if data is not ready. Default: `0` (not to wait)
|
||||
- `wait_ms` Millisecond to wait if data is not ready. Optional, defaults to 0 (not to wait) if omitted.
|
||||
|
||||
#### Returns
|
||||
Data read from data-in pin. If data is not ready in `wait_ms` millisecond, less than `size` bytes can be returned.
|
||||
|
||||
|
||||
## i2s.write()
|
||||
Write to I2S bus
|
||||
Write to I2S bus.
|
||||
|
||||
#### Syntax
|
||||
`i2s.write( i2s_num, size[, wait_ms] )`
|
||||
`i2s.write(i2s_num, data)`
|
||||
|
||||
#### Parameters
|
||||
- `adc_number` Only `adc.ADC1` now
|
||||
- `size` Bytes to send
|
||||
- `wait_ms` Millisecond to wait if DMA buffer is full. Default: `0` (not to wait)
|
||||
- `i2s_num` I2S peripheral 0 or 1
|
||||
- `data` string containing I2S stream data
|
||||
|
||||
#### Returns
|
||||
Integer, bytes wrote to buffer.
|
||||
`nil`
|
||||
|
||||
An error is thrown in case of invalid parameters or if the channel failed.
|
||||
|
|
|
|||
Loading…
Reference in New Issue