From dc334f87a6c564797f0fb394b3a349e48473f37b Mon Sep 17 00:00:00 2001
From: Nathaniel Wesley Filardo <nwfilardo@gmail.com>
Date: Fri, 18 Sep 2020 22:46:32 +0100
Subject: [PATCH] uart: expose fifo depth counters (#3177)

---
 app/modules/uart.c   | 26 ++++++++++++++++++++++++++
 docs/modules/uart.md | 14 ++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/app/modules/uart.c b/app/modules/uart.c
index 6f2c80ab..2229861c 100644
--- a/app/modules/uart.c
+++ b/app/modules/uart.c
@@ -142,6 +142,27 @@ static int l_uart_write( lua_State* L )
   return 0;
 }
 
+#define DIR_RX 0
+#define DIR_TX 1
+
+static int l_uart_fifodepth( lua_State* L )
+{
+  int id  = luaL_optinteger( L, 1, 0 );
+  if ((id != 0) && (id != 1))
+    return luaL_argerror(L, 1, "Bad UART id; must be 0 or 1");
+
+  int dir = luaL_optinteger( L, 2, 0 );
+  if ((dir != DIR_RX) && (dir != DIR_TX))
+    return luaL_argerror(L, 2, "Bad direction; must be DIR_RX or DIR_TX");
+
+  int reg = READ_PERI_REG(UART_STATUS(id));
+  int rsh = reg >> ((dir == DIR_RX) ? UART_RXFIFO_CNT_S : UART_TXFIFO_CNT_S);
+  int rm  = rsh &  ((dir == DIR_RX) ? UART_RXFIFO_CNT   : UART_TXFIFO_CNT  );
+
+  lua_pushinteger(L, rm);
+  return 1;
+}
+
 // Module function map
 LROT_BEGIN(uart, NULL, 0)
   LROT_FUNCENTRY( setup, l_uart_setup )
@@ -149,12 +170,17 @@ LROT_BEGIN(uart, NULL, 0)
   LROT_FUNCENTRY( write, l_uart_write )
   LROT_FUNCENTRY( on, l_uart_on )
   LROT_FUNCENTRY( alt, l_uart_alt )
+  LROT_FUNCENTRY( fifodepth, l_uart_fifodepth )
+
   LROT_NUMENTRY( STOPBITS_1, PLATFORM_UART_STOPBITS_1 )
   LROT_NUMENTRY( STOPBITS_1_5, PLATFORM_UART_STOPBITS_1_5 )
   LROT_NUMENTRY( STOPBITS_2, PLATFORM_UART_STOPBITS_2 )
   LROT_NUMENTRY( PARITY_NONE, PLATFORM_UART_PARITY_NONE )
   LROT_NUMENTRY( PARITY_EVEN, PLATFORM_UART_PARITY_EVEN )
   LROT_NUMENTRY( PARITY_ODD, PLATFORM_UART_PARITY_ODD )
+
+  LROT_NUMENTRY( DIR_RX, DIR_RX )
+  LROT_NUMENTRY( DIR_TX, DIR_TX )
 LROT_END(uart, NULL, 0)
 
 
diff --git a/docs/modules/uart.md b/docs/modules/uart.md
index 617cfef6..41eff203 100644
--- a/docs/modules/uart.md
+++ b/docs/modules/uart.md
@@ -145,3 +145,17 @@ Write string or byte to the UART.
 uart.write(0, "Hello, world\n")
 ```
 
+## uart.fifodepth()
+
+Report the depth, in bytes, of TX or RX hardware queues associated with the
+UART.
+
+#### Syntax
+`uart.fifodepth(id, dir)`
+
+#### Parameters
+- `id` UART id (0 or 1).
+- `dir` `uart.DIR_RX` for the RX FIFO, `uart.DIR_TX` for TX FIFO.
+
+#### Returns
+The number of bytes in the selected FIFO.