From e16204d4f4213c284976c00a251a08fd5dfc67a4 Mon Sep 17 00:00:00 2001 From: Jason Follas Date: Sat, 2 Apr 2016 13:26:07 -0400 Subject: [PATCH] Corrected SPI CPOL/CPHA relationships * Corrected CPOL/CPHA relationships * Simplified to remove duplicated code * Removed comments about when MISO is sampled. ESP seems to sample MISO on same clock edge as when MOSI is set. --- app/driver/spi.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/app/driver/spi.c b/app/driver/spi.c index fbac77e2..92c4ee05 100644 --- a/app/driver/spi.c +++ b/app/driver/spi.c @@ -72,18 +72,25 @@ void spi_master_init(uint8 spi_no, unsigned cpol, unsigned cpha, uint32_t clock_ SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CS_SETUP|SPI_CS_HOLD|SPI_RD_BYTE_ORDER|SPI_WR_BYTE_ORDER|SPI_DOUTDIN); - //set clock polarity (Reference: http://bbs.espressif.com/viewtopic.php?f=49&t=1570) + // set clock polarity (Reference: http://bbs.espressif.com/viewtopic.php?f=49&t=1570) + // phase is dependent on polarity. See Issue #1161 if (cpol == 1) { SET_PERI_REG_MASK(SPI_PIN(spi_no), SPI_IDLE_EDGE); } else { CLEAR_PERI_REG_MASK(SPI_PIN(spi_no), SPI_IDLE_EDGE); } - + //set clock phase - if (cpha == 1) { - SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CK_OUT_EDGE|SPI_CK_I_EDGE); + if (cpha == cpol) { + // Mode 3: MOSI is set on falling edge of clock + // Mode 0: MOSI is set on falling edge of clock + CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_CK_OUT_EDGE); + SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CK_I_EDGE); } else { - CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_CK_OUT_EDGE|SPI_CK_I_EDGE); + // Mode 2: MOSI is set on rising edge of clock + // Mode 1: MOSI is set on rising edge of clock + SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CK_OUT_EDGE); + CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_CK_I_EDGE); } CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_FLASH_MODE|SPI_USR_MISO|SPI_USR_ADDR|SPI_USR_COMMAND|SPI_USR_DUMMY);