143 lines
5.4 KiB
C
143 lines
5.4 KiB
C
/*
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u8g_dev_ssd1309_128x64.c
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Universal 8bit Graphics Library
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Copyright (c) 2012, olikraus@gmail.com
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this list
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of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or other
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materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "u8g.h"
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#define WIDTH 128
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#define HEIGHT 64
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#define PAGE_HEIGHT 8
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/* ssd1309 ini sequence*/
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static const uint8_t u8g_dev_ssd1309_128x64_init_seq[] PROGMEM={
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
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U8G_ESC_CS(1), /* enable chip */
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0xfd,0x12, /*Command Lock */
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0xae, /*Set Display Off */
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0xd5,0xa0, /*set Display Clock Divide Ratio/Oscillator Frequency */
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0xa8,0x3f, /*Set Multiplex Ratio */
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0x3d,0x00, /*Set Display Offset*/
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0x40, /*Set Display Start Line*/
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0xa1, /*Set Segment Re-Map*/
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0xc8, /*Set COM Output Scan Direction*/
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0xda,0x12, /*Set COM Pins Hardware Configuration*/
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0x81,0xdf, /*Set Current Control */
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0xd9,0x82, /*Set Pre-Charge Period */
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0xdb,0x34, /*Set VCOMH Deselect Level */
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0xa4, /*Set Entire Display On/Off */
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0xa6, /*Set Normal/Inverse Display*/
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U8G_ESC_VCC(1), /*Power up VCC & Stabilized */
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U8G_ESC_DLY(50),
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0xaf, /*Set Display On */
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U8G_ESC_DLY(50),
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_END /* end of sequence */
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};
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/* select one init sequence here */
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#define u8g_dev_ssd1309_128x64_init_seq u8g_dev_ssd1309_128x64_init_seq
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static const uint8_t u8g_dev_ssd1309_128x64_data_start[] PROGMEM = {
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_CS(1), /* enable chip */
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0x010, /* set upper 4 bit of the col adr to 0 */
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0x000, /* set lower 4 bit of the col adr to 4 */
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U8G_ESC_END /* end of sequence */
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};
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static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_CS(1), /* enable chip */
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0x0ae, /* display off */
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_END /* end of sequence */
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};
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static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
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U8G_ESC_ADR(0), /* instruction mode */
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U8G_ESC_CS(1), /* enable chip */
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0x0af, /* display on */
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U8G_ESC_DLY(50), /* delay 50 ms */
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U8G_ESC_CS(0), /* disable chip */
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U8G_ESC_END /* end of sequence */
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};
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uint8_t u8g_dev_ssd1309_128x64_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
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{
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switch(msg)
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{
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case U8G_DEV_MSG_INIT:
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u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1309_128x64_init_seq);
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break;
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case U8G_DEV_MSG_STOP:
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break;
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case U8G_DEV_MSG_PAGE_NEXT:
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{
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u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1309_128x64_data_start);
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u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (SSD1306) */
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u8g_SetAddress(u8g, dev, 1); /* data mode */
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if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
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return 0;
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u8g_SetChipSelect(u8g, dev, 0);
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}
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break;
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case U8G_DEV_MSG_CONTRAST:
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u8g_SetChipSelect(u8g, dev, 1);
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u8g_SetAddress(u8g, dev, 0); /* instruction mode */
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u8g_WriteByte(u8g, dev, 0x081);
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u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) ); /* 11 Jul 2015: fixed contrast calculation */
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u8g_SetChipSelect(u8g, dev, 0);
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return 1;
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case U8G_DEV_MSG_SLEEP_ON:
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
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return 1;
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case U8G_DEV_MSG_SLEEP_OFF:
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
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return 1;
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}
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return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
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}
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U8G_PB_DEV(u8g_dev_ssd1309_128x64_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1309_128x64_fn, U8G_COM_HW_SPI);
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U8G_PB_DEV(u8g_dev_ssd1309_128x64_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1309_128x64_fn, U8G_COM_SW_SPI);
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U8G_PB_DEV(u8g_dev_ssd1309_128x64_i2c, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1309_128x64_fn, U8G_COM_SSD_I2C);
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