mirror of https://github.com/joan2937/pigpio
Save and restore PWM, PCM, and clock state
This prevents pigpio wave output from disrupting sound output performed at a later point. Issue: joan2937/pigpio#567
This commit is contained in:
Diomidis Spinellis
parent
3e0a5085f1
commit
7ea7a4e438
190
pigpio.c
190
pigpio.c
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@ -893,6 +893,8 @@ Assumes two counters per block. Each counter 4 * 16 (16^4=65536)
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#define PI_MAX_PATH 512
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#define SAVED_CLK_NUMBER 5
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/* typedef ------------------------------------------------------- */
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typedef void (*callbk_t) ();
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@ -1218,6 +1220,37 @@ typedef struct
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unsigned size; /* in bytes */
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} DMAMem_t;
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typedef struct {
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// PWM: https://datasheets.raspberrypi.com/bcm2835/bcm2835-peripherals.pdf#page=141
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uint32_t pwm_state_saved;
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uint32_t pwm_ctl;
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uint32_t pwm_sta;
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uint32_t pwm_rng1;
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uint32_t pwm_dmac;
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// PCM: https://datasheets.raspberrypi.com/bcm2835/bcm2835-peripherals.pdf#page=125
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uint32_t pcm_state_saved;
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uint32_t pcm_cs;
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uint32_t pcm_fifo;
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uint32_t pcm_mode;
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uint32_t pcm_rxc;
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uint32_t pcm_txc;
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uint32_t pcm_dreq;
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uint32_t pcm_inten;
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uint32_t pcm_intstc;
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uint32_t pcm_gray;
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// Clocks: https://datasheets.raspberrypi.com/bcm2835/bcm2835-peripherals.pdf#page=107
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struct {
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uint32_t state_saved;
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uint32_t ctl_addr;
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uint32_t div_addr;
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uint32_t ctl;
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uint32_t div;
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} clk[SAVED_CLK_NUMBER];
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} pulse_modulation_state_t;
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/* global -------------------------------------------------------- */
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/* initialise once then preserve */
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@ -1412,8 +1445,11 @@ static unsigned old_mode_amosi;
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static uint32_t old_spi_cntl0;
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static uint32_t old_spi_cntl1;
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static pulse_modulation_state_t old_pms;
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static uint32_t bscFR;
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/* const --------------------------------------------------------- */
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static const uint8_t clkDef[PI_MAX_GPIO + 1] =
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@ -1883,6 +1919,7 @@ static int myDoCommand(uintptr_t *p, unsigned bufSize, char *buf)
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int masked;
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res = 0;
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DBG(DBG_USER, "cmd=%d", p[0]);
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switch (p[0])
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{
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case PI_CMD_BC1:
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@ -7884,6 +7921,16 @@ static void initPWM(unsigned bits)
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{
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DBG(DBG_STARTUP, "bits=%d", bits);
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if (!old_pms.pwm_state_saved)
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{
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DBG(DBG_USER, "Save PWM state");
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old_pms.pwm_ctl = pwmReg[PWM_CTL];
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old_pms.pwm_sta = pwmReg[PWM_STA];
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old_pms.pwm_rng1 = pwmReg[PWM_RNG1];
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old_pms.pwm_dmac = pwmReg[PWM_DMAC];
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old_pms.pwm_state_saved = 1;
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}
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/* reset PWM */
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pwmReg[PWM_CTL] = 0;
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@ -7923,10 +7970,75 @@ static void initPWM(unsigned bits)
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/* ----------------------------------------------------------------------- */
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static void restorePulseModulationState(void)
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{
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DBG(DBG_USER, "Restore state");
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if (old_pms.pwm_state_saved)
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{
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DBG(DBG_USER, "Restore PWM state");
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pwmReg[PWM_CTL] = 0; // Reset
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pwmReg[PWM_STA] = old_pms.pwm_sta;
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pwmReg[PWM_RNG1] = old_pms.pwm_rng1;
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pwmReg[PWM_DMAC] = old_pms.pwm_dmac;
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pwmReg[PWM_CTL] = PWM_CTL_CLRF1; // Clear FIFO
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pwmReg[PWM_CTL] = old_pms.pwm_ctl;
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}
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if (old_pms.pcm_state_saved)
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{
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DBG(DBG_USER, "Restore PCM state");
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pcmReg[PCM_CS] = 0; // Disable to modify
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pcmReg[PCM_FIFO] = old_pms.pcm_fifo;
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pcmReg[PCM_MODE] = old_pms.pcm_mode;
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pcmReg[PCM_RXC] = old_pms.pcm_rxc;
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pcmReg[PCM_TXC] = old_pms.pcm_txc;
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pcmReg[PCM_DREQ] = old_pms.pcm_dreq;
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pcmReg[PCM_INTEN] = old_pms.pcm_inten;
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pcmReg[PCM_INTSTC] = old_pms.pcm_intstc;
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pcmReg[PCM_GRAY] = old_pms.pcm_gray;
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pcmReg[PCM_CS] = old_pms.pcm_cs; // Enable original state
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}
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for (int clock = 0; clock < SAVED_CLK_NUMBER; clock++)
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if (old_pms.clk[clock].state_saved)
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{
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DBG(DBG_USER, "Restore clock %d state", clock);
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clkReg[old_pms.clk[clock].div_addr] = (BCM_PASSWD | old_pms.clk[clock].div);
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usleep(10);
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clkReg[old_pms.clk[clock].ctl_addr] = (BCM_PASSWD | old_pms.clk[clock].ctl);
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usleep(10);
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clkReg[old_pms.clk[clock].ctl_addr] |= (BCM_PASSWD | CLK_CTL_ENAB);
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}
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waveClockInited = 0;
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PWMClockInited = 0;
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}
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/* ----------------------------------------------------------------------- */
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static void initPCM(unsigned bits)
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{
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DBG(DBG_STARTUP, "bits=%d", bits);
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if (!old_pms.pcm_state_saved)
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{
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DBG(DBG_USER, "Save PCM state");
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old_pms.pcm_fifo = pcmReg[PCM_FIFO];
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old_pms.pcm_mode = pcmReg[PCM_MODE];
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old_pms.pcm_rxc = pcmReg[PCM_RXC];
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old_pms.pcm_txc = pcmReg[PCM_TXC];
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old_pms.pcm_dreq = pcmReg[PCM_DREQ];
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old_pms.pcm_inten = pcmReg[PCM_INTEN];
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old_pms.pcm_intstc = pcmReg[PCM_INTSTC];
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old_pms.pcm_gray = pcmReg[PCM_GRAY];
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old_pms.pcm_cs = pcmReg[PCM_CS];
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old_pms.pcm_state_saved = 1;
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}
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/* disable PCM so we can modify the regs */
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pcmReg[PCM_CS] = 0;
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@ -7975,12 +8087,39 @@ static void initPCM(unsigned bits)
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/* ----------------------------------------------------------------------- */
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static int getClkIndex(int clkCtl)
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{
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switch (clkCtl)
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{
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case CLK_GP0_CTL: return 0;
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case CLK_GP1_CTL: return 1;
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case CLK_GP2_CTL: return 2;
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case CLK_PWMCTL: return 3;
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case CLK_PCMCTL: return 4;
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}
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return 0;
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}
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/* ----------------------------------------------------------------------- */
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static void initHWClk
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(int clkCtl, int clkDiv, int clkSrc, int divI, int divF, int MASH)
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{
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DBG(DBG_INTERNAL, "ctl=%d div=%d src=%d /I=%d /f=%d M=%d",
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clkCtl, clkDiv, clkSrc, divI, divF, MASH);
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int clock = getClkIndex(clkCtl);
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if (!old_pms.clk[clock].state_saved)
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{
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DBG(DBG_USER, "Save clock %d state", clock);
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old_pms.clk[clock].ctl_addr = clkCtl;
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old_pms.clk[clock].div_addr = clkDiv;
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// Keep MASH, FLIP, and SRC
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old_pms.clk[clock].ctl = (clkReg[clkCtl] & 0b11100001111);
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old_pms.clk[clock].div = clkReg[clkDiv];
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old_pms.clk[clock].state_saved = 1;
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}
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/* kill the clock if busy, anything else isn't reliable */
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if (clkReg[clkCtl] & CLK_CTL_BUSY)
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@ -8084,6 +8223,12 @@ static void initDMAgo(volatile uint32_t *dmaAddr, uint32_t cbAddr)
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/* ----------------------------------------------------------------------- */
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void gpioInternalRestorePulseModulationState(void)
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{
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}
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/* ----------------------------------------------------------------------- */
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static void initClearGlobals(void)
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{
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int i;
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@ -8908,6 +9053,7 @@ void gpioTerminate(void)
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signalUninstaller();
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restorePulseModulationState();
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initReleaseResources();
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fflush(NULL);
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@ -12388,6 +12534,7 @@ int gpioNotifyClose(unsigned handle)
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gpioNotify[handle].state = PI_NOTIFY_CLOSING;
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intNotifyBits();
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restorePulseModulationState();
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if (gpioCfg.ifFlags & PI_DISABLE_ALERT)
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{
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@ -14238,6 +14385,49 @@ int gpioCfgSetInternals(uint32_t cfgVal)
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return 0;
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}
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/* ----------------------------------------------------------------------- */
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uint32_t gpioInternalGetReg(int regId)
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{
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DBG(DBG_USER, "");
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switch (regId)
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{
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case 0: return pwmReg[PWM_CTL];
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case 1: return pwmReg[PWM_STA];
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case 2: return pwmReg[PWM_RNG1];
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case 3: return pwmReg[PWM_DMAC];
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case 10: return pcmReg[PCM_CS];
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case 11: return pcmReg[PCM_FIFO];
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case 12: return pcmReg[PCM_MODE];
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case 13: return pcmReg[PCM_RXC];
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case 14: return pcmReg[PCM_TXC];
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case 15: return pcmReg[PCM_DREQ];
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case 16: return pcmReg[PCM_INTEN];
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case 17: return pcmReg[PCM_INTSTC];
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case 18: return pcmReg[PCM_GRAY];
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case 20: return clkReg[CLK_GP0_CTL];
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case 21: return clkReg[CLK_GP0_DIV];
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case 30: return clkReg[CLK_GP1_CTL];
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case 31: return clkReg[CLK_GP1_DIV];
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case 40: return clkReg[CLK_GP2_CTL];
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case 41: return clkReg[CLK_GP2_DIV];
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case 50: return clkReg[CLK_PWMCTL];
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case 51: return clkReg[CLK_PWMDIV];
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case 60: return clkReg[CLK_PCMCTL];
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case 61: return clkReg[CLK_PCMDIV];
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default:
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SOFT_ERROR(PI_BAD_PARAM, "bad register id (%d)", regId);
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return -1;
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}
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}
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/* include any user customisations */
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69
x_pigpio.c
69
x_pigpio.c
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@ -382,6 +382,39 @@ To the lascivious pleasing of a lute.\n\
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t5_count = 0;
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// Save current register values
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extern uint32_t gpioInternalGetReg(int regId);
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uint32_t old_pwm_ctl = gpioInternalGetReg(0);
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uint32_t old_pwm_sta = gpioInternalGetReg(1);
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uint32_t old_pwm_rng = gpioInternalGetReg(2);
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uint32_t old_pwm_dmac = gpioInternalGetReg(3);
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uint32_t old_pcm_cs = gpioInternalGetReg(10);
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uint32_t old_pcm_fifo = gpioInternalGetReg(11);
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uint32_t old_pcm_mode = gpioInternalGetReg(12);
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uint32_t old_pcm_rxc = gpioInternalGetReg(13);
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uint32_t old_pcm_txc = gpioInternalGetReg(14);
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uint32_t old_pcm_dreq = gpioInternalGetReg(15);
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uint32_t old_pcm_inten = gpioInternalGetReg(16);
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uint32_t old_pcm_intstc = gpioInternalGetReg(17);
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uint32_t old_pcm_gray = gpioInternalGetReg(18);
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uint32_t old_pwm_clk_gp0_ctl = gpioInternalGetReg(20);
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uint32_t old_pwm_clk_gp0_div = gpioInternalGetReg(21);
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uint32_t old_pwm_clk_gp1_ctl = gpioInternalGetReg(30);
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uint32_t old_pwm_clk_gp1_div = gpioInternalGetReg(31);
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uint32_t old_pwm_clk_gp2_ctl = gpioInternalGetReg(40);
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uint32_t old_pwm_clk_gp2_div = gpioInternalGetReg(41);
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uint32_t old_pwm_clk_ctl = gpioInternalGetReg(50);
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uint32_t old_pwm_clk_div = gpioInternalGetReg(51);
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uint32_t old_pcm_clk_ctl = gpioInternalGetReg(60);
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uint32_t old_pcm_clk_div = gpioInternalGetReg(61);
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gpioSetAlertFunc(GPIO, t5cbf);
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gpioSetMode(GPIO, PI_OUTPUT);
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@ -505,6 +538,42 @@ To the lascivious pleasing of a lute.\n\
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CHECK(5, 28, t5_count, 5, 1, "callback count==");
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gpioSetAlertFunc(GPIO, NULL);
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extern void gpioInternalRestorePulseModulationState(void);
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gpioInternalRestorePulseModulationState();
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// Check register values
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CHECK(5, 29, gpioInternalGetReg(0), old_pwm_ctl, 0, "PWM CTL=");
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const uint32_t pwm_sta_mask = ~0b1111111100;
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CHECK(5, 30, gpioInternalGetReg(1) & pwm_sta_mask, old_pwm_sta & pwm_sta_mask, 0, "PWM STA=");
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CHECK(5, 31, gpioInternalGetReg(2), old_pwm_rng, 0, "PWM RNG=");
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CHECK(5, 32, gpioInternalGetReg(3), old_pwm_dmac, 0, "PWM DMAC=");
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const uint32_t pcm_cs_mask = ~0b1001110000000000;
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CHECK(5, 33, gpioInternalGetReg(10) & pcm_cs_mask, old_pcm_cs & pcm_cs_mask, 0, "PCM CS=");
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CHECK(5, 34, gpioInternalGetReg(11), old_pcm_fifo, 0, "PCM FIFO=");
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CHECK(5, 35, gpioInternalGetReg(12), old_pcm_mode, 0, "PCM MODE=");
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CHECK(5, 36, gpioInternalGetReg(13), old_pcm_rxc, 0, "PCM RXC=");
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CHECK(5, 37, gpioInternalGetReg(14), old_pcm_txc, 0, "PCM TXC=");
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CHECK(5, 38, gpioInternalGetReg(15), old_pcm_dreq, 0, "PCM DREQ=");
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CHECK(5, 39, gpioInternalGetReg(16), old_pcm_inten, 0, "PCM INTEN=");
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CHECK(5, 40, gpioInternalGetReg(17), old_pcm_intstc, 0, "PCM INTSTC=");
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CHECK(5, 41, gpioInternalGetReg(18), old_pcm_gray, 0, "PCM GRAY=");
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CHECK(5, 42, gpioInternalGetReg(20), old_pwm_clk_gp0_ctl , 0, "GP0 CLK CTL=");
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CHECK(5, 43, gpioInternalGetReg(21), old_pwm_clk_gp0_div , 0, "GP0 CLK DIV=");
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CHECK(5, 44, gpioInternalGetReg(30), old_pwm_clk_gp1_ctl , 0, "GP1 CLK CTL=");
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CHECK(5, 45, gpioInternalGetReg(31), old_pwm_clk_gp1_div , 0, "GP1 CLK DIV=");
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CHECK(5, 46, gpioInternalGetReg(40), old_pwm_clk_gp2_ctl , 0, "GP2 CLK CTL=");
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CHECK(5, 47, gpioInternalGetReg(41), old_pwm_clk_gp2_div , 0, "GP2 CLK DIV=");
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CHECK(5, 48, gpioInternalGetReg(50), old_pwm_clk_ctl , 0, "PWM CLK CTL=");
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CHECK(5, 49, gpioInternalGetReg(51), old_pwm_clk_div , 0, "PWM CLK DIV=");
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CHECK(5, 50, gpioInternalGetReg(60), old_pcm_clk_ctl , 0, "PCM CLK CTL=");
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CHECK(5, 51, gpioInternalGetReg(61), old_pcm_clk_div , 0, "PCM CLK DIV=");
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}
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int t6_count;
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