63 lines
1.7 KiB
Markdown
63 lines
1.7 KiB
Markdown
# ADC Module
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| Since | Origin / Contributor | Maintainer | Source |
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| :----- | :-------------------- | :---------- | :------ |
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| 2017-04-22 | [zelll](https://github.com/zelll) | [zelll](https://github.com/zelll) | [adc.c](../../components/modules/adc.c)|
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The ADC module provides access to the in-built ADC1.
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On the ESP32 there are two ADC. ADC1 has 8 channels, while ADC2 has 10 channels. Currently, only ADC1 is supported.
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## adc.setwidth()
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The configuration is in effect for all channels of ADC1
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#### Syntax
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`adc.setwidth(adc_number, bits)`
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#### Parameters
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- `adc_number` Only `adc.ADC1` now
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- `bits` One of `9`/`10`/`11`/`12`.
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#### Returns
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`nil`
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## adc.setup()
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Configuration ADC1 capture attenuation of channels
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#### Syntax
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`adc.setup(adc_number, channel, atten)`
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#### Parameters
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- `adc_number` Only `adc.ADC1` now
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- `channel` When using `adc.ADC1`: `0` to `7`. 0: GPIO36, 1: GPIO37, 2: GPIO38, 3: GPIO39, 4: GPIO32, 5: GPIO33, 6: GPIO34, 7: GPIO35
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- `atten` One of following constants
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- `adc.ATTEN_0db` The input voltage of ADC will be reduced to about 1/1 (1.1V when VDD_A=3.3V)
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- `adc.ATTEN_2_5db` The input voltage of ADC will be reduced to about 1/1.34 (1.5V when VDD_A=3.3V)
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- `adc.ATTEN_6db` The input voltage of ADC will be reduced to about 1/2 (2.2V when VDD_A=3.3V)
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- `adc.ATTEN_11db` The input voltage of ADC will be reduced to about 1/3.6 (3.9V when VDD_A=3.3V, maximum voltage is limited by VDD_A)
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#### Returns
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`nil`
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## adc.read()
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Samples the ADC. You should to call `setwidth()` before `read()`.
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#### Syntax
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`adc.read(adc_number, channel)`
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#### Parameters
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- `adc_number` Only `adc.ADC1` now
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- `channel` 0 to 7 for adc.ADC1
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#### Returns
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the sampled value (number)
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#### Example
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```lua
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val = adc.read(adc.ADC1, 0)
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```
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